Hybrid transactional memory

  • Authors:

  • Sanjeev Kumar;Michael Chu;Christopher J. Hughes;Partha Kundu;Anthony Nguyen

  • Affiliations:

  • Intel Labs, Santa Clara, CA;University of Michigan, Ann Arbor;Intel Labs, Santa Clara, CA;Intel Labs, Santa Clara, CA;Intel Labs, Santa Clara, CA

  • Venue:
  • Proceedings of the eleventh ACM SIGPLAN symposium on Principles and practice of parallel programming
  • Year:
  • 2006

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Abstract

High performance parallel programs are currently difficult to write and debug. One major source of difficulty is protecting concurrent accesses to shared data with an appropriate synchronization mechanism. Locks are the most common mechanism but they have a number of disadvantages, including possibly unnecessary serialization, and possible deadlock. Transactional memory is an alternative mechanism that makes parallel programming easier. With transactional memory, a transaction provides atomic and serializable operations on an arbitrary set of memory locations. When a transaction commits, all operations within the transaction become visible to other threads. When it aborts, all operations in the transaction are rolled back.Transactional memory can be implemented in either hardware or software. A straightforward hardware approach can have high performance, but imposes strict limits on the amount of data updated in each transaction. A software approach removes these limits, but incurs high overhead. We propose a novel hybrid hardware-software transactional memory scheme that approaches the performance of a hardware scheme when resources are not exhausted and gracefully falls back to a software scheme otherwise.