The SPARC architecture manual: version 8
The SPARC architecture manual: version 8
Transactional memory: architectural support for lock-free data structures
ISCA '93 Proceedings of the 20th annual international symposium on computer architecture
The synergy between non-blocking synchronization and operating system structure
OSDI '96 Proceedings of the second USENIX symposium on Operating systems design and implementation
Proceedings of the twentieth annual ACM symposium on Principles of distributed computing
Speculative lock elision: enabling highly concurrent multithreaded execution
Proceedings of the 34th annual ACM/IEEE international symposium on Microarchitecture
High performance dynamic lock-free hash tables and list-based sets
Proceedings of the fourteenth annual ACM symposium on Parallel algorithms and architectures
Proceedings of the twenty-first annual symposium on Principles of distributed computing
Transactional lock-free execution of lock-based programs
Proceedings of the 10th international conference on Architectural support for programming languages and operating systems
Software transactional memory for dynamic-sized data structures
Proceedings of the twenty-second annual symposium on Principles of distributed computing
DCAS is not a silver bullet for nonblocking algorithm design
Proceedings of the sixteenth annual ACM symposium on Parallelism in algorithms and architectures
Unbounded Transactional Memory
HPCA '05 Proceedings of the 11th International Symposium on High-Performance Computer Architecture
Virtualizing Transactional Memory
Proceedings of the 32nd annual international symposium on Computer Architecture
Proceedings of the eleventh ACM SIGPLAN symposium on Principles and practice of parallel programming
Testing implementations of transactional memory
Proceedings of the 15th international conference on Parallel architectures and compilation techniques
Proceedings of the 12th international conference on Architectural support for programming languages and operating systems
Architectural Support for Software Transactional Memory
Proceedings of the 39th Annual IEEE/ACM International Symposium on Microarchitecture
Solaris(TM) Performance and Tools: DTrace and MDB Techniques for Solaris 10 and OpenSolaris (Solaris Series)
Hardware atomicity for reliable software speculation
Proceedings of the 34th annual international symposium on Computer architecture
SNZI: scalable NonZero indicators
Proceedings of the twenty-sixth annual ACM symposium on Principles of distributed computing
LogTM-SE: Decoupling Hardware Transactional Memory from Caches
HPCA '07 Proceedings of the 2007 IEEE 13th International Symposium on High Performance Computer Architecture
Proceedings of the 13th ACM SIGPLAN Symposium on Principles and practice of parallel programming
ISCA '08 Proceedings of the 35th Annual International Symposium on Computer Architecture
An efficient transactional memory algorithm for computing minimum spanning forest of sparse graphs
Proceedings of the 14th ACM SIGPLAN symposium on Principles and practice of parallel programming
Early experience with a commercial hardware transactional memory implementation
Proceedings of the 14th international conference on Architectural support for programming languages and operating systems
Producing wrong data without doing anything obviously wrong!
Proceedings of the 14th international conference on Architectural support for programming languages and operating systems
Rock: A High-Performance Sparc CMT Processor
IEEE Micro
Proceedings of the 36th annual international symposium on Computer architecture
NZTM: nonblocking zero-indirection transactional memory
Proceedings of the twenty-first annual symposium on Parallelism in algorithms and architectures
Early experience with a commercial hardware transactional memory implementation
Proceedings of the 14th international conference on Architectural support for programming languages and operating systems
Simplifying concurrent algorithms by exploiting hardware transactional memory
Proceedings of the twenty-second annual ACM symposium on Parallelism in algorithms and architectures
Hybrid NOrec: a case study in the effectiveness of best effort hardware transactional memory
Proceedings of the sixteenth international conference on Architectural support for programming languages and operating systems
Adding concurrency in python using a commercial processor's hardware transactional memory support
ACM SIGARCH Computer Architecture News
On the power of hardware transactional memory to simplify memory management
Proceedings of the 30th annual ACM SIGACT-SIGOPS symposium on Principles of distributed computing
What kinds of applications can benefit from transactional memory?
ISCA'10 Proceedings of the 2010 international conference on Computer Architecture
Using hardware transactional memory to correct and simplify and readers-writer lock algorithm
Proceedings of the 18th ACM SIGPLAN symposium on Principles and practice of parallel programming
| Hi-index | 0.00 |
We report on our experience with the hardware transactional memory (HTM) feature of two revisions of a prototype multicore processor. Our experience includes a number of promising results using HTM to improve performance in a variety of contexts, and also identifies some ways in which the feature could be improved to make it even better. We give detailed accounts of our experiences, sharing techniques we used to achieve the results we have, as well as describing challenges we faced in doing so. This technical report expands on our ASPLOS paper [9], providing more detail and reporting on additional work conducted since that paper was written.