Early experience with a commercial hardware transactional memory implementation
Proceedings of the 14th international conference on Architectural support for programming languages and operating systems
Proceedings of the 36th annual international symposium on Computer architecture
NZTM: nonblocking zero-indirection transactional memory
Proceedings of the twenty-first annual symposium on Parallelism in algorithms and architectures
NOrec: streamlining STM by abolishing ownership records
Proceedings of the 15th ACM SIGPLAN Symposium on Principles and Practice of Parallel Programming
Early experience with a commercial hardware transactional memory implementation
Early experience with a commercial hardware transactional memory implementation
Dynamic filtering: multi-purpose architecture support for language runtime systems
Proceedings of the fifteenth edition of ASPLOS on Architectural support for programming languages and operating systems
Fast sort on CPUs and GPUs: a case for bandwidth oblivious SIMD sort
Proceedings of the 2010 ACM SIGMOD International Conference on Management of data
The inherent complexity of transactional memory and what to do about it
Proceedings of the 29th ACM SIGACT-SIGOPS symposium on Principles of distributed computing
Journal of Parallel and Distributed Computing
Invited paper: the inherent complexity of transactional memory and what to do about it
ICDCN'11 Proceedings of the 12th international conference on Distributed computing and networking
Hybrid NOrec: a case study in the effectiveness of best effort hardware transactional memory
Proceedings of the sixteenth international conference on Architectural support for programming languages and operating systems
Adding concurrency in python using a commercial processor's hardware transactional memory support
ACM SIGARCH Computer Architecture News
A composite and scalable cache coherence protocol for large scale CMPs
Proceedings of the international conference on Supercomputing
A case for unlimited watchpoints
ASPLOS XVII Proceedings of the seventeenth international conference on Architectural Support for Programming Languages and Operating Systems
Delegation and nesting in best-effort hardware transactional memory
Proceedings of the twenty-fourth annual ACM symposium on Parallelism in algorithms and architectures
What scientific applications can benefit from hardware transactional memory?
SC '12 Proceedings of the International Conference on High Performance Computing, Networking, Storage and Analysis
SCIN-cache: Fast speculative versioning in multithreaded cores
ACM Transactions on Architecture and Code Optimization (TACO) - Special Issue on High-Performance Embedded Architectures and Compilers
Transactional Memory Architecture and Implementation for IBM System Z
MICRO-45 Proceedings of the 2012 45th Annual IEEE/ACM International Symposium on Microarchitecture
Brief announcement: between all and nothing - versatile aborts in hardware transactional memory
Proceedings of the twenty-fifth annual ACM symposium on Parallelism in algorithms and architectures
Harmonic semi-partitioned scheduling for fixed-priority real-time tasks on multi-core platform
DATE '12 Proceedings of the Conference on Design, Automation and Test in Europe
Opportunities and pitfalls of multi-core scaling using hardware transaction memory
Proceedings of the 4th Asia-Pacific Workshop on Systems
MLP-aware dynamic instruction window resizing for adaptively exploiting both ILP and MLP
Proceedings of the 46th Annual IEEE/ACM International Symposium on Microarchitecture
| Hi-index | 0.00 |
Rock, Sun's third-generation chip-multithreading processor, contains 16 high-performance cores, each of which can support two software threads. Rock uses a novel checkpoint-based architecture to support automatic hardware scouting under a load miss, speculative out-of-order retirement of instructions, and aggressive dynamic hardware parallelization of a sequential instruction stream. It is also the first processor to support transactional memory in hardware.