Transactional memory: architectural support for lock-free data structures
ISCA '93 Proceedings of the 20th annual international symposium on computer architecture
Transactional Memory Coherence and Consistency
Proceedings of the 31st annual international symposium on Computer architecture
McRT-STM: a high performance software transactional memory system for a multi-core runtime
Proceedings of the eleventh ACM SIGPLAN symposium on Principles and practice of parallel programming
Proceedings of the 12th international conference on Architectural support for programming languages and operating systems
Architectural Support for Software Transactional Memory
Proceedings of the 39th Annual IEEE/ACM International Symposium on Microarchitecture
ATLAS: a chip-multiprocessor with transactional memory support
Proceedings of the conference on Design, automation and test in Europe
Configurable Transactional Memory
FCCM '07 Proceedings of the 15th Annual IEEE Symposium on Field-Programmable Custom Computing Machines
Dynamic performance tuning of word-based software transactional memory
Proceedings of the 13th ACM SIGPLAN Symposium on Principles and practice of parallel programming
Software Transactional Memory: Why Is It Only a Research Toy?
Queue - The Concurrency Problem
An efficient transactional memory algorithm for computing minimum spanning forest of sparse graphs
Proceedings of the 14th ACM SIGPLAN symposium on Principles and practice of parallel programming
Early experience with a commercial hardware transactional memory implementation
Proceedings of the 14th international conference on Architectural support for programming languages and operating systems
WormBench: a configurable workload for evaluating transactional memory systems
Proceedings of the 9th workshop on MEmory performance: DEaling with Applications, systems and architecture
Rock: A High-Performance Sparc CMT Processor
IEEE Micro
Evaluation of AMD's advanced synchronization facility within a complete transactional memory stack
Proceedings of the 5th European conference on Computer systems
CLOMP: accurately characterizing OpenMP application overheads
IWOMP'08 Proceedings of the 4th international conference on OpenMP in a new era of parallelism
Transactional Memory, 2nd Edition
Transactional Memory, 2nd Edition
Eigenbench: A simple exploration tool for orthogonal TM characteristics
IISWC '10 Proceedings of the IEEE International Symposium on Workload Characterization (IISWC'10)
Benchmarking modern multiprocessors
Benchmarking modern multiprocessors
DISC'06 Proceedings of the 20th international conference on Distributed Computing
A case for including transactions in OpenMP
IWOMP'10 Proceedings of the 6th international conference on Beyond Loop Level Parallelism in OpenMP: accelerators, Tasking and more
A case for including transactions in OpenMP II: hardware transactional memory
IWOMP'12 Proceedings of the 8th international conference on OpenMP in a Heterogeneous World
Evaluation of Blue Gene/Q hardware support for transactional memories
Proceedings of the 21st international conference on Parallel architectures and compilation techniques
A case for including transactions in OpenMP II: hardware transactional memory
IWOMP'12 Proceedings of the 8th international conference on OpenMP in a Heterogeneous World
SC '13 Proceedings of the International Conference on High Performance Computing, Networking, Storage and Analysis
Evaluation of two formulations of the conjugate gradients method with transactional memory
Euro-Par'13 Proceedings of the 19th international conference on Parallel Processing
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Achieving efficient and correct synchronization of multiple threads is a difficult and error-prone task at small scale and, as we march towards extreme scale computing, will be even more challenging when the resulting application is supposed to utilize millions of cores efficiently. Transactional Memory (TM) is a promising technique to ease the burden on the programmer, but only recently has become available on commercial hardware in the new Blue Gene/Q system and hence the real benefit for realistic applications has not been studied yet. This paper presents the first performance results of TM embedded into OpenMP on a prototype system of BG/Q and characterizes code properties that will likely lead to benefits when augmented with TM primitives. We first study the influence of thread count, environment variables and memory layout on TM performance and identify code properties that will yield performance gains with TM. Second, we evaluate the combination of OpenMP with multiple synchronization primitives on top of MPI to determine suitable task to thread ratios per node. Finally, we condense our findings into a set of best practices. These are applied to a Monte Carlo Benchmark and a Smoothed Particle Hydrodynamics method. In both cases an optimized TM version, executed with 64 threads on one node, outperforms a simple TM implementation. MCB with optimized TM yields a speedup of 27.45 over baseline.