A methodology for implementing highly concurrent data objects
ACM Transactions on Programming Languages and Systems (TOPLAS)
Transactional memory: architectural support for lock-free data structures
ISCA '93 Proceedings of the 20th annual international symposium on computer architecture
Speculative lock elision: enabling highly concurrent multithreaded execution
Proceedings of the 34th annual ACM/IEEE international symposium on Microarchitecture
Transactional Memory Coherence and Consistency
Proceedings of the 31st annual international symposium on Computer architecture
Architectural Semantics for Practical Transactional Memory
Proceedings of the 33rd annual international symposium on Computer Architecture
Tradeoffs in transactional memory virtualization
Proceedings of the 12th international conference on Architectural support for programming languages and operating systems
Hardware atomicity for reliable software speculation
Proceedings of the 34th annual international symposium on Computer architecture
Transactional Memory: An Overview
IEEE Micro
On the correctness of transactional memory
Proceedings of the 13th ACM SIGPLAN Symposium on Principles and practice of parallel programming
Rock: A High-Performance Sparc CMT Processor
IEEE Micro
IBM system z10 processor cache subsystem microarchitecture
IBM Journal of Research and Development
DISC'06 Proceedings of the 20th international conference on Distributed Computing
The IBM Blue Gene/Q Compute Chip
IEEE Micro
IBM zEnterprise 196 microprocessor and cache subsystem
IBM Journal of Research and Development
Structured deferral: synchronization via procrastination
Communications of the ACM
Robust architectural support for transactional memory in the power architecture
Proceedings of the 40th Annual International Symposium on Computer Architecture
Brief announcement: between all and nothing - versatile aborts in hardware transactional memory
Proceedings of the twenty-fifth annual ACM symposium on Parallelism in algorithms and architectures
Structured Deferral: Synchronization via Procrastination
Queue - Concurrency
The balancing act of choosing nonblocking features
Communications of the ACM
SC '13 Proceedings of the International Conference on High Performance Computing, Networking, Storage and Analysis
The Balancing Act of Choosing Nonblocking Features
Queue - Development
Kiln: closing the performance gap between systems with and without persistence support
Proceedings of the 46th Annual IEEE/ACM International Symposium on Microarchitecture
Eliminating global interpreter locks in ruby through hardware transactional memory
Proceedings of the 19th ACM SIGPLAN symposium on Principles and practice of parallel programming
Scaling existing lock-based applications with lock elision
Communications of the ACM
Scaling Existing Lock-based Applications with Lock Elision
Queue - Performance
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We present the introduction of transactional memory into the next generation IBM System z CPU. We first describe the instruction-set architecture features, including requirements for enterprise-class software RAS. We then describe the implementation in the IBM zEnterprise EC12 (zEC12) microprocessor generation, focusing on how transactional memory can be embedded into the existing cache design and multiprocessor shared-memory infrastructure. We explain practical reasons behind our choices. The zEC12 system is available since September 2012.