IBM system z10 processor cache subsystem microarchitecture

  • Authors:

  • P. Mak;C. R. Walters;G. E. Strait

  • Affiliations:

  • IBM Systems and Technology Group, Poughkeepsie, New York;IBM Systems and Technology Group, Poughkeepsie, New York;IBM Systems and Technology Group, Poughkeepsie, New York

  • Venue:
  • IBM Journal of Research and Development
  • Year:
  • 2009

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Abstract

With the introduction of the high-frequency IBM System z10™ processor design, a new, robust cache hierarchy was needed to enable up to 80 of these processors aggregated into a tightly coupled symmetric multiprocessor (SMP) system to reach their performance potential. Typically, each time the processor frequency increases by a significant factor, as did the z10™ processor over the predecessor IBM System z9® processor, the access time of data, as measured by the number of processor cycles beyond the level 1 cache on an identical processor cache subsystem, would increase proportionally as well because the flight time on the chip interconnects across multiple hardware packaging levels has stayed relatively constant in nanoseconds. To address the latency scaling problem and the increased demand of the larger 80-way SMP size, the z10 processor cache subsystem introduces new innovative concepts and solutions.