In search of clusters (2nd ed.)
In search of clusters (2nd ed.)
Computer architecture: a quantitative approach
Computer architecture: a quantitative approach
Infiniband
The integrated cluster bus for the IBM S/390 parallel Sysplex
IBM Journal of Research and Development
Self-timed interface for S/390 I/O subsystem interconnection
IBM Journal of Research and Development
IBM eServer z900 I/O subsystem
IBM Journal of Research and Development
Self-timed interface of the input/output subsystem of the IBM eServer z900
IBM Journal of Research and Development
Coupling I/O channels for the IBM eServer z900: reengineering required
IBM Journal of Research and Development
Functional verification of a frequency-programmable switch chip with asynchronous clock sections
IBM Journal of Research and Development
IBM Journal of Research and Development
IBM system z10 processor cache subsystem microarchitecture
IBM Journal of Research and Development
Design and verification of the IBM system z10 I/O subsystem chips
IBM Journal of Research and Development
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The performance of large servers is to a high degree determined by their I/O subsystems. In the z990 server, nearly all of the components in the I/O path have been considerably improved in performance, capability, and cost. A 2-GB/s enhanced self-timed interface (eSTI) was introduced which is capable of absorbing the ever-increasing data rates of modern high-speed adapters. The I/O bandwidth available from a single node (three memory bus adapter, or MBA, chips, each with four eSTI ports) now equals 48 GB/s. As a consequence, both the MBA chip and the STI multiplexer switch (STI switch) chip had to be completely redesigned. In addition to these two chips, this paper describes the eSTI design itself and the Sweep chip, which integrates the function of four bidirectional adapter chips, one switch chip, and a clock chip.