S/390 cluster technology: Parallel Sysplex
IBM Systems Journal
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Self-timed interface for S/390 I/O subsystem interconnection
IBM Journal of Research and Development
Integrated cluster bus performance for the IBM S/390 parallel Sysplex
IBM Journal of Research and Development
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IBM Journal of Research and Development
Self-timed interface for S/390 I/O subsystem interconnection
IBM Journal of Research and Development
Integrated cluster bus performance for the IBM S/390 parallel Sysplex
IBM Journal of Research and Development
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IBM Journal of Research and Development
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IBM Journal of Research and Development
Self-timed interface of the input/output subsystem of the IBM eServer z900
IBM Journal of Research and Development
Coupling I/O channels for the IBM eServer z900: reengineering required
IBM Journal of Research and Development
IBM Parallel Sysplex design for the IBM z196 system
IBM Journal of Research and Development
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IBM has developed a new S/390® Parallel Sysplex® coupling interface for the G5 server called the Integrated Cluster Bus (ICB). This interface improves the coupling efficiency by greatly reducing message-passing latency. Using the transport layer of the S/390 self-timed interface (STI) introduced in the G3 server, ICB adds channel function to the hub chip to allow a more direct interconnection between S/390 servers. This new channel has the same function as the present intersystem channel (ISC), but because it is integrated into the hub chip and therefore requires no additional components, its reliability is much better than that of the ISC. Since the ISC transmits data at a peak rate of 106 MB/s over distances exceeding ten kilometers and the ICB transmits data at a peak rate of 333 MB/s at distances of ten meters, the ISC is still required for the more geographically dispersed Parallel Sysplexes, whereas the ICB is well suited to the machine room, where multiple servers can be interconnected by ten-meter cables. This paper describes the design approach for the ICB. It describes the fundamental message-passing requirements of the Parallel Sysplex and how they are implemented in very complex yet compact hardware in the server's hub chip.