Processor subsystem interconnect architecture for a large symmetric multiprocessing system

  • Authors:

  • P. Mak;G. E. Strait;M. A. Blake;K. W. Kark;V. K. Papazova;A. E. Seigler;G. A. Van Huben;L. Wang;G. C. Wellwood

  • Affiliations:

  • IBM Systems and Technology Group, 2455 South Road, Poughkeepsie, New York;IBM Systems and Technology Group, 2455 South Road, Poughkeepsie, New York;IBM Systems and Technology Group, 2455 South Road, Poughkeepsie, New York;IBM Systems and Technology Group, 2455 South Road, Poughkeepsie, New York;IBM Systems and Technology Group, 2455 South Road, Poughkeepsie, New York;IBM Systems and Technology Group, 2455 South Road, Poughkeepsie, New York;IBM Systems and Technology Group, 2455 South Road, Poughkeepsie, New York;IBM Systems and Technology Group, 2455 South Road, Poughkeepsie, New York;IBM Systems and Technology Group, 2455 South Road, Poughkeepsie, New York

  • Venue:
  • IBM Journal of Research and Development
  • Year:
  • 2004

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Abstract

Integral to the significant capacity growth of the IBM eServerTM z990 (the eighth-generation zSeries® CMOS-based server) from its predecessor z900 system is the interconnect architecture, which tightly couples 48 customer CPUs in the system. A major attribute of this architecture is a new "hot swap" feature which improves zSeries system availability for customers by permitting the substitution or addition of a field-replaceable unit (FRU) in the processor subsystem without requiring the system to be powered down. The novel two-level interconnect architecture contains a distributed switch which connects up to four processor-memory nodes in book packages. The book packages, which are also FRUs, are connected in a dual concentric ring topology at the second-level (L2) interconnect. This architecture also contains an integrated 32-MB L2 cache and central switch connecting up to eight dual-core processor chips in a star topology at the first-level interconnect inside one of these nodes. This paper describes the bus protocol on the second-level interconnect, the cache coherency management throughout the storage hierarchy, and the ring topology reconfiguration for hot swap. Also described is a memory, power management scheme to support the power demand from the 48 CPUs and up to 256 GB of memory.