Functional verification of the IBM system z10 processor chipset

Authors:
C. A. Krygowski;D. G. Bair;R. M. Gott;M. H. Decker;A. V. Giri;C. Habermann;M. Heizmann;S. Letz;W. J. Lewis;S. M. Licker;H. Mallar;E. C. McCain;W. Roesner;N. Siddique;A. E. Seigler;B. W. Thompto;K. Weber;R. Winkelmann
Affiliations:
IBM Systems and Technology Group, Poughkeepsie, New York;IBM Systems and Technology Group, Poughkeepsie, New York;IBM Systems and Technology Group, Poughkeepsie, New York;IBM Systems and Technology Group, Poughkeepsie, New York;IBM Systems and Technology Group, Austin, Texas;IBM Systems and Technology Group, Boeblingen, Germany;IBM Systems and Technology Group, Poughkeepsie, New York;IBM Deutschland Entwicklung GmbH, Boeblingen, Germany;IBM Systems and Technology Group, Poughkeepsie, New York;IBM Systems and Technology Group, Poughkeepsie, New York;IBM Systems and Technology Group, Poughkeepsie, New York;IBM Systems and Technology Group, Poughkeepsie, New York;IBM Systems and Technology Group, Austin, Texas;IBM Systems and Technology Group, Poughkeepsie, New York;IBM Systems and Technology Group, Poughkeepsie, New York;IBM Systems and Technology Group, Austin, Texas;IBM Deutschland Entwicklung GmbH, Boeblingen, Germany;IBM Deutschland Entwicklung GmbH, Boeblingen, Germany
Venue:
IBM Journal of Research and Development
Year:
2009

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Abstract

This paper describes the comprehensive verification effort of the IBM System z10™ processor chipset, which consists of the z10™ quad-core central processor chip and the companion z10 symmetric multiprocessor (SMP) chip. The z10 processor chipset represented a significant redesign of its predecessor and thus presented a new challenge to ensure complete functional correctness of the product before the construction of actual system hardware. The z10 microprocessor pipeline was completely redesigned to support a doubling of the operating frequency. It also includes new hardware performance features, such as enhanced branch prediction, a reoptimized cache hierarchy, hardware-based prefetching, and a hardware implementation of decimal floating-point arithmetic in IEEE formats. In addition, there were significant hardware changes in the SMP storage hierarchy for optimized data latency performance. These changes include a new system topology, interprocessor book protocol, larger SMP size, and various aggressive cache ownership schemes. Key verification innovations are described, and a direct relationship to improved z10 system quality is provided for most cases.