Key advances in the presilicon functional verification of the IBM zEnterprise microprocessor and storage hierarchy

  • Authors:

  • C. A. Krygowski;E. Almog;D. G. Bair;R. Breil;G. Dittmann;R. M. Gott;W. J. Lewis;A. D. Shah;B. W. Thompto

  • Affiliations:

  • IBM Systems and Technology Group, Poughkeepsie, NY;Freescale Semiconductor, Austin, TX;IBM Systems and Technology Group, Poughkeepsie, NY;IBM Systems and Technology Group, IBM Deutschland Research and Development GmbH, Germany;IBM Systems and Technology Group, IBM Deutschland Research and Development GmbH, Boeblingen, Germany;IBM Systems and Technology Group, Poughkeepsie, NY;IBM Systems and Technology Group, Poughkeepsie, NY;IBM Systems and Technology Group, Poughkeepsie, NY;IBM Systems and Technology Group, Austin, TX

  • Venue:
  • IBM Journal of Research and Development
  • Year:
  • 2012

Quantified Score

Hi-index 0.00

Visualization

Abstract

This paper highlights key advances in the presilicon verification effort of the IBM zEnterprise® 196 (z196) microprocessor and storage hierarchy. It focuses on the unique set of verification challenges as well as the process innovations that address them. At the time of product launch, the z196 system represented the industry's fastest and most scalable enterprise system, with up to 80 customer-configurable out-of-order core processors operating at 5.2 GHz. In addition to offering industry-leading performance, the z196 system builds upon its leadership in reliability by introducing a new redundant array of independent memory (RAIM) technology into its memory subsystem. The new product features in this system drove innovations in all aspects of processor functional verification, including stimulus generation, functional checking, debugging, and coverage. A new hybrid RAIM verification methodology, which includes both formal and random methods, is described. Many process and methodology improvements were made to improve developmental collaboration across a global team. These enhancements include a simulation development environment that uses common shared components across functional partitions, as well as a shared cache loader that was used across multiple environments. We also present a self-configuring test-case generation process that focused on the coverage of functional stimulus.