ESA/390 interpretive-execution architecture, foundation for VM/ESA
IBM Systems Journal
Writing testbenches: functional verification of HDL models
Writing testbenches: functional verification of HDL models
X-Gen: a random test-case generator for systems and SoCs
HLDVT '02 Proceedings of the Seventh IEEE International High-Level Design Validation and Test Workshop
Verification Methodology Manual for SystemVerilog
Verification Methodology Manual for SystemVerilog
Intelligent interleaving of scenarios: a novel approach to system level test generation
Proceedings of the 44th annual Design Automation Conference
Role of the verification team throughout the ASIC development life cycle
Proceedings of the 46th Annual Design Automation Conference
IBM Journal of Research and Development
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Verifying new hardware systems is a daunting task. To reduce the amount of effort involved, verification teams attempt to reuse as much verification IP as possible. We introduce a novel approach for test generation that enables the reuse of verification IP to verify new functionality. This method applies to a significant category of features, which are variations on the functionality of an existing design. Our method is being successfully used in the verification of high-end IBM servers: System p and System z. We compared our technique to alternative approaches and show that it achieves the best quality while reducing manual effort.