Symbolic Boolean manipulation with ordered binary-decision diagrams
ACM Computing Surveys (CSUR)
Computer-aided verification of coordinating processes: the automata-theoretic approach
Computer-aided verification of coordinating processes: the automata-theoretic approach
High performance BDD package by exploiting memory hierarchy
DAC '96 Proceedings of the 33rd annual Design Automation Conference
Breadth-first manipulation of very large binary-decision diagrams
ICCAD '93 Proceedings of the 1993 IEEE/ACM international conference on Computer-aided design
Safe BDD minimization using don't cares
DAC '97 Proceedings of the 34th annual Design Automation Conference
Cycle-based symbolic simulation of gate-level synchronous circuits
Proceedings of the 36th annual ACM/IEEE Design Automation Conference
Formal verification using parametric representations of Boolean constraints
Proceedings of the 36th annual ACM/IEEE Design Automation Conference
Efficient state representation for symbolic simulation
Proceedings of the 39th annual Design Automation Conference
Symbolic Simulation with Approximate Values
FMCAD '00 Proceedings of the Third International Conference on Formal Methods in Computer-Aided Design
Verification of Synchronous Sequential Machines Based on Symbolic Execution
Proceedings of the International Workshop on Automatic Verification Methods for Finite State Systems
Counterexample-Guided Abstraction Refinement
CAV '00 Proceedings of the 12th International Conference on Computer Aided Verification
Property Checking via Structural Analysis
CAV '02 Proceedings of the 14th International Conference on Computer Aided Verification
Efficient Scheduling Techniques for ROBDD Construction
VLSID '99 Proceedings of the 12th International Conference on VLSI Design - 'VLSI for the Information Appliance'
A SAT-based algorithm for reparameterization in symbolic simulation
Proceedings of the 41st annual Design Automation Conference
Automatic Formal Verification of Fused-Multiply-Add FPUs
Proceedings of the conference on Design, Automation and Test in Europe - Volume 2
CHARME'05 Proceedings of the 13 IFIP WG 10.5 international conference on Correct Hardware Design and Verification Methods
Robust Boolean reasoning for equivalence checking and functional property verification
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Evaluating coverage of error detection logic for soft errors using formal methods
Proceedings of the conference on Design, automation and test in Europe: Proceedings
Functional verification of the IBM system z10 processor chipset
IBM Journal of Research and Development
Speeding up model checking by exploiting explicit and hidden verification constraints
Proceedings of the Conference on Design, Automation and Test in Europe
Large-scale application of formal verification: from fiction to fact
Proceedings of the 2010 Conference on Formal Methods in Computer-Aided Design
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Most computer-aided design frameworks rely upon building BDD representations from netlist descriptions. In this paper, we present efficient algorithms for building BDDs from netlists. First, we introduce a dynamic scheduling algorithm for building BDDs for gates of the netlist, using an efficient hybrid of depth- and breadth-first traversal, and constant propagation. Second, we introduce a dynamic algorithm for optimally leveraging constraints and invariants as don't-cares during the building of BDDs for intermediate gates. Third, we present an automated and complete case splitting approach which is triggered by resource bounds. Unlike prior work in case splitting which focused upon variable cofactoring, our approach leverages the full power of our don't-caring solution and intelligently selects arbitrary functions to apply as constraints to maximally reduce peak BDD size while minimizing the number of cases to be explored. While these techniques may be applied to enhance the building of BDDs for arbitrary applications, we focus on their application within cycle-based symbolic simulation. Experiments confirm the effectiveness of these synergistic approaches in enabling optimal BDD building with minimal resources.