Formal Methods in System Design
Automatic Formal Verification of Fused-Multiply-Add FPUs
Proceedings of the conference on Design, Automation and Test in Europe - Volume 2
Functional formal verification on designs of pSeries microprocessors and communication subsystems
IBM Journal of Research and Development - POWER5 and packaging
Enabling Large-Scale Pervasive Logic Verification through Multi-Algorithmic Formal Reasoning
FMCAD '06 Proceedings of the Formal Methods in Computer Aided Design
ACL2SIX: A Hint used to Integrate a Theorem Prover and an Automated Verification Tool
FMCAD '06 Proceedings of the Formal Methods in Computer Aided Design
A Practical Introduction to PSL (Series on Integrated Circuits and Systems)
A Practical Introduction to PSL (Series on Integrated Circuits and Systems)
Formal Verification of Partial Good Self-Test Fencing Structures
FMCAD '07 Proceedings of the Formal Methods in Computer Aided Design
Transaction Based Modeling and Verification of Hardware Protocols
FMCAD '07 Proceedings of the Formal Methods in Computer Aided Design
Functional Verification of Power Gated Designs by Compositional Reasoning
CAV '08 Proceedings of the 20th international conference on Computer Aided Verification
Invariant-strengthened elimination of dependent state elements
Proceedings of the 2008 International Conference on Formal Methods in Computer-Aided Design
Optimal constraint-preserving netlist simplification
Proceedings of the 2008 International Conference on Formal Methods in Computer-Aided Design
Functional verification of the POWER4 microprocessor and POWER4 multiprocessor systems
IBM Journal of Research and Development
Speculative reduction-based scalable redundancy identification
Proceedings of the Conference on Design, Automation and Test in Europe
Formal verification of arbiters using property strengthening and underapproximations
Proceedings of the 2010 Conference on Formal Methods in Computer-Aided Design
Coping with Moore's law (and more): supporting arrays in state-of-the-art model checkers
Proceedings of the 2010 Conference on Formal Methods in Computer-Aided Design
Automatic verification of estimate functions with polynomials of bounded functions
Proceedings of the 2010 Conference on Formal Methods in Computer-Aided Design
Efficient symbolic simulation via dynamic scheduling, don't caring, and case splitting
CHARME'05 Proceedings of the 13 IFIP WG 10.5 international conference on Correct Hardware Design and Verification Methods
Exploiting constraints in transformation-based verification
CHARME'05 Proceedings of the 13 IFIP WG 10.5 international conference on Correct Hardware Design and Verification Methods
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Formal verification has matured considerably as a verification discipline in the past couple of decades, becoming a mainstream technology in industrial design and verification methodologies and processes. In this paper we chronicle the evolution of formal verification at IBM from being a specialized side activity with a narrow focus, to achieving a broad-based usage as a core verification technology helping to significantly improve design and verification productivity. We showcase what is possible in the application of formal verification in a commercial/industrial setting by highlighting the success we had in leveraging the technology extensively on IBM's POWER7™ microprocessor and systems. We touch upon the methodology and execution aspects of the unprecedented use of formal verification on the POWER7 program, and depict ways in which the technology positively impacted pre-silicon design quality and facilitated root causing of bug escapes to silicon. Furthermore, we outline where we see applied formal verification evolving towards at IBM, and the challenges thereof.