A Practical Approach to Word Level Model Checking of Industrial Netlists
CAV '08 Proceedings of the 20th international conference on Computer Aided Verification
BackSpace: formal analysis for post-silicon debug
Proceedings of the 2008 International Conference on Formal Methods in Computer-Aided Design
Word-level sequential memory abstraction for model checking
Proceedings of the 2008 International Conference on Formal Methods in Computer-Aided Design
Word level bitwidth reduction for unbounded hardware model checking
Formal Methods in System Design
Large-scale application of formal verification: from fiction to fact
Proceedings of the 2010 Conference on Formal Methods in Computer-Aided Design
Functional verification of the IBM POWER7 microprocessor and POWER7 multiprocessor systems
IBM Journal of Research and Development
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Pervasive Logic is a broad term applied to the variety of logic present in hardware designs, yet not a part of their primary functionality. Examples of pervasive logic include initialization and self-test logic. Because pervasive logic is intertwined with the functionality of chips, the verification of such logic tends to require very deep sequential analysis of very large slices of the design. For this reason, pervasive logic verification has hitherto been a task for which formal algorithms were not considered applicable. In this paper, we discuss several pervasive logic verification tasks for which we have found the proper combination of algorithms to enable formal analysis. We describe the nature of these verification tasks, and the testbenches used in the verification process. We furthermore discuss the types of algorithms needed to solve these verification tasks, and the type of tuning we performed on these algorithms to enable this analysis.