Skip lists: a probabilistic alternative to balanced trees
Communications of the ACM
Better verification through symmetry
Formal Methods in System Design - Special issue on symmetry in automatic verification
An improved equivalence algorithm
Communications of the ACM
CAV '02 Proceedings of the 14th International Conference on Computer Aided Verification
Automatic Datapath Abstraction In Hardware Systems
Proceedings of the 7th International Conference on Computer Aided Verification
A Delay Model and Speculative Architecture for Pipelined Routers
HPCA '01 Proceedings of the 7th International Symposium on High-Performance Computer Architecture
Enabling Large-Scale Pervasive Logic Verification through Multi-Algorithmic Formal Reasoning
FMCAD '06 Proceedings of the Formal Methods in Computer Aided Design
BAT: the bit-level analysis tool
CAV'07 Proceedings of the 19th international conference on Computer aided verification
Scalable liveness checking via property-preserving transformations
Proceedings of the Conference on Design, Automation and Test in Europe
Learning conditional abstractions
Proceedings of the International Conference on Formal Methods in Computer-Aided Design
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In this paper we present a word-level model checking method that attempts to speed up safety property checking of industrial netlists. Our aim is to construct an algorithm that allows us to check both bounded and unbounded properties using standard bit-level model checking methods as back-end decision procedures, while incurring minimum runtime penalties for designs that are unsuited to our analysis. We do this by combining modifications of several previously known techniques into a static abstraction algorithm which is guaranteed to produce bit-level netlists that are as small or smaller than the original bitblasted designs. We evaluate our algorithm on several challenging hardware components.