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A Practical Approach to Word Level Model Checking of Industrial Netlists
CAV '08 Proceedings of the 20th international conference on Computer Aided Verification
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Word-level sequential memory abstraction for model checking
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A Network Congestion-Aware Memory Controller
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Abstract: This paper introduces a router delay model that accurately models key aspects of modern routers.The model accounts for the pipeline nature of contemporary routers,the specific flow control method employed,the delay of the flow- control credit path,and the sharing of crossbar ports across virtual channels.Motivate by this model,we introduce a microarchitecture for a speculative virtual-channel router that significantly reduces its router latency to that of a wormhole router.Simulations using our pipelined model give results that differ considerably from the commonly-assumed unit-latency 'model which is unreasonably optimistic.Using realistic pipeline models,we compare wormhole [6 ]and virtual-channel flow control [4 ].Our results show that a speculative virtual-channel router has the same per-hop router latency as a wormhole router,while improving throughput by up to 40%.