VirtualClock: a new traffic control algorithm for packet-switched networks
ACM Transactions on Computer Systems (TOCS)
QoS provisioning in clusters: an investigation of Router and NIC design
ISCA '01 Proceedings of the 28th annual international symposium on Computer architecture
MediaWorm: A QoS Capable Router Architecture for Clusters
IEEE Transactions on Parallel and Distributed Systems
Current issues in packet switch design
ACM SIGCOMM Computer Communication Review
MMR: A High-Performance Multimedia Router - Architecture and Design Trade-Offs
HPCA '99 Proceedings of the 5th International Symposium on High Performance Computer Architecture
A Delay Model and Speculative Architecture for Pipelined Routers
HPCA '01 Proceedings of the 7th International Symposium on High-Performance Computer Architecture
IEEE Transactions on Parallel and Distributed Systems
HPCA '05 Proceedings of the 11th International Symposium on High-Performance Computer Architecture
The Network Processing Forum switch fabric benchmark specifications: an overview
IEEE Network: The Magazine of Global Internetworking
Scalable Low-Cost QoS Support for Single-chip Switches
ICPADS '06 Proceedings of the 12th International Conference on Parallel and Distributed Systems - Volume 1
A low-cost strategy to provide full QoS support in Advanced Switching networks
Journal of Systems Architecture: the EUROMICRO Journal
A New Cost-Effective Technique for QoS Support in Clusters
IEEE Transactions on Parallel and Distributed Systems
Providing Full QoS with 2 VCs in High-Speed Switches
Information Networking. Towards Ubiquitous Networking and Services
Euro-Par'06 Proceedings of the 12th international conference on Parallel Processing
A hardware NIC scheduler to guarantee qos on high performance servers
ISPA'06 Proceedings of the 4th international conference on Parallel and Distributed Processing and Applications
High-throughput differentiated service provision router architecture for wireless network-on-chip
International Journal of High Performance Systems Architecture
Integrated QoS provision and congestion management for interconnection networks
Euro-Par'07 Proceedings of the 13th international Euro-Par conference on Parallel Processing
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Current interconnect standards providing hardware support for quality of service (QoS) consider up to 16 virtual channels (VCs) for this purpose. However, most implementations do not offer so many VCs because they increase the complexity of the switch and the scheduling delays. In this paper, we show that this number of VCs can be significantly reduced. Some of the scheduling decisions made at network interfaces can be easily reused at switches without significantly altering the global behavior. Specifically, we show that it is enough to use two VCs for QoS purposes at each switch port, thereby simplifying the design and reducing its cost.