A hardware NIC scheduler to guarantee qos on high performance servers

Authors:
J. M. Claver;M. Canseco;P. Agustí;G. León
Affiliations:
Department of Computer Science and Engineering, University Jaume I, Castellón, Spain;Department of Computer Science and Engineering, University Jaume I, Castellón, Spain;Department of Computer Science and Engineering, University Jaume I, Castellón, Spain;Department of Computer Science and Engineering, University Jaume I, Castellón, Spain
Venue:
ISPA'06 Proceedings of the 4th international conference on Parallel and Distributed Processing and Applications
Year:
2006

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Abstract

In this paper we present the architecture and implementation of a hardware NIC scheduler to guarantee QoS on servers for high speed LAN/SAN. Our proposal employs a programmable logic device based on an FPGA in order to store and update connection states, and to decide what data stream is to be sent next. The network architecture is connection-oriented and reliable, based on credit flow control. The architecture scales from 4 to 32 streams using a Xilinx Virtex 2000E. It supports links with speeds in the order of Gbps while, maintaining the delay and jitter constrains for the QoS streams.