A Cost-Effective Hardware Link Scheduling Algorithm for the Multimedia Router (MMR)

Authors:
Blanca Caminero;C. Carrión;Francisco J. Quiles;José Duato;Sudhakar Yalamanchili
Affiliations:
-;-;-;-;-
Venue:
ICN '01 Proceedings of the First International Conference on Networking-Part 2
Year:
2001

Citing 0
Cited 5

Investigating Switch Scheduling Algorithms to Support QoS in the Multimedia Router

IPDPS '02 Proceedings of the 16th International Parallel and Distributed Processing Symposium
Traffic Scheduling Solutions with QoS Support for an Input-Buffered MultiMedia Router

IEEE Transactions on Parallel and Distributed Systems
MMR: A MultiMedia Router architecture to support hybrid workloads

Journal of Parallel and Distributed Computing
A new hardware efficient link scheduling algorithm to guarantee qos on clusters

Euro-Par'05 Proceedings of the 11th international Euro-Par conference on Parallel Processing
A hardware NIC scheduler to guarantee qos on high performance servers

ISPA'06 Proceedings of the 4th international conference on Parallel and Distributed Processing and Applications

Quantified Score

Hi-index	0.00

Visualization

Abstract

The primary objective of the Multimedia Router (MMR) project is the design and implementation of a compact router optimized for multimedia applications. The router is targeted for use in cluster and LAN interconnection networks, which offer different constraints and therefore differing router solutions than WANs. One of the key elements in order to achieve these goals is the scheduling algorithm. In a previous paper, the authors have proposed a link/switch scheduling algorithm capable of providing different QoS guarantees to flows as needed. This work focuses on the reduction of the hardware complexity necessary to implement such algorithm. A novel priority algorithm is presented, and its hardware complexity is compared to that of the original proposal.