A Family of Fault-Tolerant Routing Protocols for Direct Multiprocessor Networks
IEEE Transactions on Parallel and Distributed Systems
Symmetric Crossbar Arbiters for VLSI Communication Switches
IEEE Transactions on Parallel and Distributed Systems
ATLAS: A Single-Chip ATM Switch for NOWs
CANPC '97 Proceedings of the First International Workshop on Communication and Architectural Support for Network-Based Parallel Computing
Performance Evaluation of the Multimedia Router with MPEG-2 Video Traffic
CANPC '99 Proceedings of the Third International Workshop on Network-Based Parallel Computing: Communication, Architecture, and Applications
A Cost-Effective Hardware Link Scheduling Algorithm for the Multimedia Router (MMR)
ICN '01 Proceedings of the First International Conference on Networking-Part 2
MMR: A High-Performance Multimedia Router - Architecture and Design Trade-Offs
HPCA '99 Proceedings of the 5th International Symposium on High Performance Computer Architecture
Switch Scheduling in the Multimedia Router (MMR)
IPDPS '00 Proceedings of the 14th International Symposium on Parallel and Distributed Processing
Bandwidth and latency guarantees in low-cost, high-performance networks
Bandwidth and latency guarantees in low-cost, high-performance networks
Scheduling nonuniform traffic in high speed packet switches and routers
Scheduling nonuniform traffic in high speed packet switches and routers
MMR: A MultiMedia Router architecture to support hybrid workloads
Journal of Parallel and Distributed Computing
A two-stage hardware scheduler combining greedy and optimal scheduling
Journal of Parallel and Distributed Computing
A hardware NIC scheduler to guarantee qos on high performance servers
ISPA'06 Proceedings of the 4th international conference on Parallel and Distributed Processing and Applications
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The primary objective of the Multimedia Router (MMR) project is the design and implementation of a compact router optimized for multimedia applications. The router is targeted for use in cluster and LAN interconnection networks, which offer different constraints and therefore differing router solutions than WANs. The goal is to provide architectural support to enable a range of Quality Of Service (QoS) guarantees at latencies comparable to state-of-the-art multiprocessor cut-through routers. One of the critical design parameters in order to provide this is the switch scheduling algorithm. The authors proposed in an earlier work an efficient crossbar arbitration scheme, the Candidate-Order Arbiter algorithm. In this paper, the performance obtained with this proposal is analyzed and compared to other well-known scheme. The results show that QoS may not be guaranteed by using a switch scheduling algorithm targeted only to maximize crossbar utilization. Moreover, simulations show that our approach is a suitable algorithm to guarantee high bandwidth utilization, up to 78%, while still providing QoS to both CBR and VBR traffic.