The Designer's Guide to VHDL
Architecture and Hardware for Scheduling Gigabit Packet Streams
HOTI '02 Proceedings of the 10th Symposium on High Performance Interconnects HOT Interconnects
A Reprogrammable FPGA-Based ATM Traffic Generator
GLSVLSI '96 Proceedings of the 6th Great Lakes Symposium on VLSI
From VHDL Register Transfer Level to SystemC Transaction Level Modeling: A Comparative Case Study
SBCCI '03 Proceedings of the 16th symposium on Integrated circuits and systems design
Rapid System Prototyping with FPGAs: Accelerating the Design Process
Rapid System Prototyping with FPGAs: Accelerating the Design Process
A Fast Emulation-Based NoC Prototyping Framework
RECONFIG '08 Proceedings of the 2008 International Conference on Reconfigurable Computing and FPGAs
A hardware NIC scheduler to guarantee qos on high performance servers
ISPA'06 Proceedings of the 4th international conference on Parallel and Distributed Processing and Applications
Hardware implementation study of several new egress link scheduling algorithms
Journal of Parallel and Distributed Computing
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Nowadays, high performance System and Local Area Networks (SAN/LAN) have to serve heterogeneous traffic consisting of information flows with different bandwidth and latency requirements. This makes it necessary to provide Quality of Service (QoS) and optimize the design of network components. In this paper we present a hardware tool designed to analyze the performance of QoS networks, under given traffic conditions and server models. In particular, a reprogrammable multimedia traffic Generator/Monitor platform has been built. This permits prototyping the communication system of a high speed LAN/SAN on a single FPGA device. Hence, it can be used at design to produce more efficient devices. To illustrate the applicability of the platform we have used the Simple Multimedia Router (SMMR), an existing proposal to provide QoS. The modular structure of the tool and the fact that it has been implemented on an FPGA using a high level hardware programming language makes it flexible, scalable and easy to reconfigure. Besides, the architecture and implementation can be adapted to be used in more recent QoS NoC environments.