Analysis and simulation of a fair queueing algorithm
SIGCOMM '89 Symposium proceedings on Communications architectures & protocols
Journal of the ACM (JACM)
IEEE/ACM Transactions on Networking (TON)
Efficient fair queueing using deficit round robin
SIGCOMM '95 Proceedings of the conference on Applications, technologies, architectures, and protocols for computer communication
Efficient fair queueing using deficit round-robin
IEEE/ACM Transactions on Networking (TON)
Proceedings of the 1996 ACM SIGMETRICS international conference on Measurement and modeling of computer systems
Hierarchical packet fair queueing algorithms
IEEE/ACM Transactions on Networking (TON)
Latency-rate servers: a general model for analysis of traffic scheduling algorithms
IEEE/ACM Transactions on Networking (TON)
Gigabit Ethernet: Technology and Applications for High-Speed LANs
Gigabit Ethernet: Technology and Applications for High-Speed LANs
The Designer's Guide to VHDL
Advanced Research Issues for Tomorrow's Multimedia Networks
ITCC '01 Proceedings of the International Conference on Information Technology: Coding and Computing
Traffic scheduling in packet-switched networks: analysis, design, and implementation
Traffic scheduling in packet-switched networks: analysis, design, and implementation
End-to-end delay service in high-speed packet networks using earliest deadline first scheduling
End-to-end delay service in high-speed packet networks using earliest deadline first scheduling
Fair scheduling with tunable latency: a round-robin approach
IEEE/ACM Transactions on Networking (TON)
Interconnect-Aware Coherence Protocols for Chip Multiprocessors
Proceedings of the 33rd annual international symposium on Computer Architecture
A Framework to Provide Quality of Service over Advanced Switching
IEEE Transactions on Parallel and Distributed Systems
Providing QoS with the Deficit Table Scheduler
IEEE Transactions on Parallel and Distributed Systems
A reconfigurable platform for evaluating the performance of QoS networks
Journal of Systems Architecture: the EUROMICRO Journal
WF2Q: worst-case fair weighted fair queueing
INFOCOM'96 Proceedings of the Fifteenth annual joint conference of the IEEE computer and communications societies conference on The conference on computer communications - Volume 1
Hardware-efficient fair queueing architectures for high-speed networks
INFOCOM'96 Proceedings of the Fifteenth annual joint conference of the IEEE computer and communications societies conference on The conference on computer communications - Volume 2
QoS in Packet Networks
New directions in communications (or which way to the information age?)
IEEE Communications Magazine
An overview of QoS capabilities in infiniband, advanced switching interconnect, and ethernet
IEEE Communications Magazine
Measuring the Gap Between FPGAs and ASICs
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
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The provision of Quality of Service (QoS) in interconnection networks is required for new multimedia and time-sensitive applications, which are very important for recent utility computing data centers (UCDCs) using high performance networks. These interconnection networks support switch-based principles and establish high demands in terms of bandwidth, time-delay, and delivery over short distances. A key component for networks with QoS support is the egress link scheduling algorithm. Apart from providing a good performance in terms of, for example, good end-to-end delay (also called latency) and fair bandwidth allocation, an ideal scheduling algorithm implemented in a high-performance network with QoS support should satisfy another important property which is to have a low computational and implementation complexity. In this paper, we propose specific implementations (taking into account the characteristics of current high performance networks) of several fair-queuing scheduling algorithms and compare their complexity in terms of silicon area and computation delay. In order to carry out this comparison, we have devised our own hardware comparison methodology. Following this methodology, we have performed our own hardware implementation for the different schedulers. We have modeled the schedulers using the Handel-C language and employed the DK design suite tool from Celoxica in order to obtain hardware estimates on silicon area and arbitration time.