Hardware Implementation Study of the SCFQ-CA and DRR-CA Scheduling Algorithms
Euro-Par '09 Proceedings of the 15th International Euro-Par Conference on Parallel Processing
Hardware implementation study of several new egress link scheduling algorithms
Journal of Parallel and Distributed Computing
| Hi-index | 0.00 |
Abstract: Computer networks require complex solutions for traffic shaping and for bandwidth management on links and switching nodes, in order to provide a reliable QoS-based infrastructure for multimedia and bandwidth-on-demand applications. A simpler and lightweight solution could be reached by a new approach in designing the network protocols. The evolution of the hardware technology will make available faster processing units and larger memories for network devices; this could lead to a radical change of paradigm in network design if a long term research plan for innovative network architectures became popular in the research community. The wide variety of arguments to be investigated requires a multidisciplinary approach, possibly involving several research groups worldwide from research institutions and industrial R&D. The main purpose of this article is to suggest some guidelines for designing an innovative architecture for computer networks. Our proposal descends from a circumstantial survey of existing technologies, and offers a general framework for individuating and approaching research topics of common interest in the networking environment.