Analysis and simulation of a fair queueing algorithm
SIGCOMM '89 Symposium proceedings on Communications architectures & protocols
IEEE/ACM Transactions on Networking (TON)
Efficient fair queueing using deficit round robin
SIGCOMM '95 Proceedings of the conference on Applications, technologies, architectures, and protocols for computer communication
Latency-rate servers: a general model for analysis of traffic scheduling algorithms
IEEE/ACM Transactions on Networking (TON)
Advanced Research Issues for Tomorrow's Multimedia Networks
ITCC '01 Proceedings of the International Conference on Information Technology: Coding and Computing
End-to-end delay service in high-speed packet networks using earliest deadline first scheduling
End-to-end delay service in high-speed packet networks using earliest deadline first scheduling
Interconnect-Aware Coherence Protocols for Chip Multiprocessors
Proceedings of the 33rd annual international symposium on Computer Architecture
A Framework to Provide Quality of Service over Advanced Switching
IEEE Transactions on Parallel and Distributed Systems
Hardware-efficient fair queueing architectures for high-speed networks
INFOCOM'96 Proceedings of the Fifteenth annual joint conference of the IEEE computer and communications societies conference on The conference on computer communications - Volume 2
An overview of QoS capabilities in infiniband, advanced switching interconnect, and ethernet
IEEE Communications Magazine
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The provision of Quality of Service (QoS) in computing and communication environments has been the focus of much research in industry and academia during the last decades. A key component for networks with QoS support is the egress link scheduling algorithm. Apart from providing a good performance in terms of, for example, good end-to-end delay and fair bandwidth allocation, an ideal scheduling algorithm implemented in a high-performance network with QoS support should satisfy other important property which is to have a low computational and implementation complexity. This is especially important in high-performance networks due to their high speed and because switches are usually implemented in a single chip. In [7] we proposed the Self-Clocked Fair Queuing Credit Aware (SCFQ-CA) and the Deficit Round Robin Credit Aware (DRR-CA) schedulers in order to adapt the SCFQ and DRR algorithms to networks with a link-level flow control mechanism. In this paper, we propose specific implementations of these two schedulers taking into account the characteristics of current high-performance networks. Moreover, we compare the complexity of these two algorithms in terms of silicon area and computation delay. In order to carry out this comparison, we have performed our own hardware implementation for the different schedulers. We have modeled the schedulers using the Handel-C language and employed the DK design suite tool from Celoxica in order to obtain hardware estimates on silicon area and arbitration time.