Interconnection Networks: An Engineering Approach
Interconnection Networks: An Engineering Approach
Current issues in packet switch design
ACM SIGCOMM Computer Communication Review
MMR: A High-Performance Multimedia Router - Architecture and Design Trade-Offs
HPCA '99 Proceedings of the 5th International Symposium on High Performance Computer Architecture
Dynamic Voltage Scaling with Links for Power Optimization of Interconnection Networks
HPCA '03 Proceedings of the 9th International Symposium on High-Performance Computer Architecture
IEEE Transactions on Parallel and Distributed Systems
Providing full qos support in clusters using only two VCs at the switches
HiPC'05 Proceedings of the 12th international conference on High Performance Computing
The Network Processing Forum switch fabric benchmark specifications: an overview
IEEE Network: The Magazine of Global Internetworking
| Hi-index | 0.00 |
Virtual channels (VCs) are a popular solution for the provision of quality of service (QoS). Current interconnect standards propose 16 or even more VCs for this purpose. However, most commercial implementations do not offer so many VCs because it is too expensive in terms of silicon area. Therefore, a reduction of the number of VCs necessary to support QoS can be very helpful in the switch design and implementation. We have shown that this number of VCs can be reduced if the system is considered as a whole rather than each element being taken separately. Some of the scheduling decisions made at network interfaces can be easily reused at switches without significantly altering the global behavior. In this paper, our aim is to explore the scalability of the technique, considering the restrictions of the final chip implementation.