The iSLIP scheduling algorithm for input-queued switches
IEEE/ACM Transactions on Networking (TON)
Low-power system-level design of VLSI packet switching fabrics
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Matching output queueing with a combined input/output-queued switch
IEEE Journal on Selected Areas in Communications
Scalable Low-Cost QoS Support for Single-chip Switches
ICPADS '06 Proceedings of the 12th International Conference on Parallel and Distributed Systems - Volume 1
Overall Blocking Behavior Analysis of General Banyan-Based Optical Switching Networks
IEEE Transactions on Parallel and Distributed Systems
A low-cost strategy to provide full QoS support in Advanced Switching networks
Journal of Systems Architecture: the EUROMICRO Journal
A New Cost-Effective Technique for QoS Support in Clusters
IEEE Transactions on Parallel and Distributed Systems
Performance of a speculative transmission scheme for scheduling-latency reduction
IEEE/ACM Transactions on Networking (TON)
On guaranteed smooth switching for buffered crossbar switches
IEEE/ACM Transactions on Networking (TON)
MOTIM: an industrial application using nocs
Proceedings of the 21st annual symposium on Integrated circuits and system design
Trends in highly scalable crossbar-based packet switch architecture
Computer Communications
Feedback-based scheduling for load-balanced two-stage switches
IEEE/ACM Transactions on Networking (TON)
Dynamic topologies for sustainable and energy efficient traffic routing
Computer Networks: The International Journal of Computer and Telecommunications Networking
QoS support for video transmission in high-speed interconnects
HPCC'06 Proceedings of the Second international conference on High Performance Computing and Communications
Providing full qos support in clusters using only two VCs at the switches
HiPC'05 Proceedings of the 12th international conference on High Performance Computing
Euro-Par'06 Proceedings of the 12th international conference on Parallel Processing
High-throughput differentiated service provision router architecture for wireless network-on-chip
International Journal of High Performance Systems Architecture
Efficient buffering and scheduling for a single-chip crosspoint-queued switch
Proceedings of the eighth ACM/IEEE symposium on Architectures for networking and communications systems
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Addressing the ever growing capacity demand for packet switches, current research focuses on scheduling algorithms or buffer bandwidth reductions. Although these topics remain relevant, our position is that the primary design focus for systems beyond 1 Tb/s must be shifted to aspects resulting from packaging disruptions. Based on trends such as increased link rates and improved CMOS technologies, we derive new design factors for such switch fabrics. For instance, we argue that the packet round-trip transmission time within the fabric has become a major design parameter. Furthermore, we observe that high-speed fabrics have become extremely dependent on serial I/O technology that is both high speed and high density. Finally, we conclude that in developing the architecture, packaging constraints must be put first and not as an afterthought, which also applies to solving the tremendous power consumption challenges.