An integrated solution for QoS provision and congestion management in high-performance interconnection networks using deterministic source-based routing

Authors:
Juan A. Villar;Pedro J. García;Francisco J. Alfaro;José L. Sánchez;Francisco J. Quiles
Affiliations:
Department of Computing Systems, Escuela Superior de Ingeniería Informática, University of Castilla-La Mancha, Albacete, Spain;Department of Computing Systems, Escuela Superior de Ingeniería Informática, University of Castilla-La Mancha, Albacete, Spain;Department of Computing Systems, Escuela Superior de Ingeniería Informática, University of Castilla-La Mancha, Albacete, Spain;Department of Computing Systems, Escuela Superior de Ingeniería Informática, University of Castilla-La Mancha, Albacete, Spain;Department of Computing Systems, Escuela Superior de Ingeniería Informática, University of Castilla-La Mancha, Albacete, Spain
Venue:
The Journal of Supercomputing
Year:
2013

Citing 27
Cited 0

Fat-trees: universal networks for hardware-efficient supercomputing

IEEE Transactions on Computers
Dynamically-Allocated Multi-Queue Buffers for VLSI Communication Switches

IEEE Transactions on Computers
High-speed switch scheduling for local-area networks

ACM Transactions on Computer Systems (TOCS)
Using a Multipath Network for Reducing the Effects of Hot Spots

IEEE Transactions on Parallel and Distributed Systems
Efficient fair queueing using deficit round robin

SIGCOMM '95 Proceedings of the conference on Applications, technologies, architectures, and protocols for computer communication
Architectural requirements and scalability of the NAS parallel benchmarks

SC '99 Proceedings of the 1999 ACM/IEEE conference on Supercomputing
Deadlock-Free Adaptive Routing in Multicomputer Networks Using Virtual Channels

IEEE Transactions on Parallel and Distributed Systems
Current issues in packet switch design

ACM SIGCOMM Computer Communication Review
Dynamic Voltage Scaling with Links for Power Optimization of Interconnection Networks

HPCA '03 Proceedings of the 9th International Symposium on High-Performance Computer Architecture
Self-Tuned Congestion Control for Multiprocessor Networks

HPCA '01 Proceedings of the 7th International Symposium on High-Performance Computer Architecture
Performance of Various Computers Using Standard Linear Equations Software

Performance of Various Computers Using Standard Linear Equations Software
Congestion Control in InfiniBand Networks

HOTI '05 Proceedings of the 13th Symposium on High Performance Interconnects
Globally Adaptive Load-Balanced Routing on Tori

IEEE Computer Architecture Letters
Efficient, Scalable Congestion Management for Interconnection Networks

IEEE Micro
A New Cost-Effective Technique for QoS Support in Clusters

IEEE Transactions on Parallel and Distributed Systems
Congestion management for non-blocking clos networks

Proceedings of the 3rd ACM/IEEE Symposium on Architecture for networking and communications systems
A Switch Architecture Guaranteeing QoS Provision and HOL Blocking Elimination

IEEE Transactions on Parallel and Distributed Systems
Adding mechanisms for QoS to a network-on-chip

Proceedings of the 22nd Annual Symposium on Integrated Circuits and System Design: Chip on the Dunes
Buffer Management Strategies to Reduce HoL Blocking

IEEE Transactions on Parallel and Distributed Systems
An efficient strategy for reducing head-of-line blocking in fat-trees

Euro-Par'10 Proceedings of the 16th international Euro-Par conference on Parallel processing: Part II
vFtree - A Fat-Tree Routing Algorithm Using Virtual Lanes to Alleviate Congestion

IPDPS '11 Proceedings of the 2011 IEEE International Parallel & Distributed Processing Symposium
Combining Congested-Flow Isolation and Injection Throttling in HPC Interconnection Networks

ICPP '11 Proceedings of the 2011 International Conference on Parallel Processing
Towards a cost-effective interconnection network architecture with qos and congestion management support

Euro-Par'06 Proceedings of the 12th international conference on Parallel Processing
INSEE: an interconnection network simulation and evaluation environment

Euro-Par'05 Proceedings of the 11th international Euro-Par conference on Parallel Processing
Weighted round-robin cell multiplexing in a general-purpose ATM switch chip

IEEE Journal on Selected Areas in Communications
Exploring the Scope of the InfiniBand Congestion Control Mechanism

IPDPS '12 Proceedings of the 2012 IEEE 26th International Parallel and Distributed Processing Symposium
Integrated QoS provision and congestion management for interconnection networks

Euro-Par'07 Proceedings of the 13th international Euro-Par conference on Parallel Processing

Quantified Score

Hi-index	0.00

Visualization

Abstract

A key element in any system based on several interconnected computing and/or storage nodes is the interconnection network. Currently, one of the main concerns of high-speed interconnection network designers is how to improve network performance while using the minimum number of network resources. In that sense, in this paper we describe an efficient switch architecture suitable for any interconnect technology implementing deterministic source-based routing. This switch architecture uses the same network resources to provide two issues that improve network performance: Congestion Management and QoS support. We also present results to compare the effectiveness of this architecture to those of other proposals typically used to provide these issues in this context. These results have been obtained for synthetic traffic and for traces from parallel benchmarks and video frames. From the results, we can conclude that in any traffic scenario, our proposal is as effective as the previous ones, while requiring fewer resources and thus being much more cost-effective.