Fat-trees: universal networks for hardware-efficient supercomputing
IEEE Transactions on Computers
Dynamically-Allocated Multi-Queue Buffers for VLSI Communication Switches
IEEE Transactions on Computers
High-speed switch scheduling for local-area networks
ACM Transactions on Computer Systems (TOCS)
Interconnection Networks: An Engineering Approach
Interconnection Networks: An Engineering Approach
k -ary n -trees: High Performance Networks for Massively Parallel Architectures
IPPS '97 Proceedings of the 11th International Symposium on Parallel Processing
A Memory-Effective Routing Strategy for Regular Interconnection Networks
IPDPS '05 Proceedings of the 19th IEEE International Parallel and Distributed Processing Symposium (IPDPS'05) - Papers - Volume 01
Destination-Based HoL Blocking Elimination
ICPADS '06 Proceedings of the 12th International Conference on Parallel and Distributed Systems - Volume 1
RECN-IQ: A Cost-Effective Input-Queued Switch Architecture with Congestion Management
ICPP '07 Proceedings of the 2007 International Conference on Parallel Processing
HiPC'08 Proceedings of the 15th international conference on High performance computing
Proceedings of the first international workshop on Network-aware data management
A new proposal to deal with congestion in InfiniBand-based fat-trees
Journal of Parallel and Distributed Computing
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The fat-tree is one of the most common topologies for the interconnection networks of PC Clusters which are currently used for high-performance parallel computing. Among other advantages, fat-trees allow the use of simple but very efficient routing schemes. One of them is a deterministic routing algorithm that has been recently proposed, offering similar (or better) performance than Adaptive Routing while reducing complexity and guaranteeing in-order packet delivery. However, as other deterministic routing proposals, this deterministic routing algorithm cannot react when high traffic loads or hot-spot traffic scenarios produce severe contention for the use of network resources, leading to the appearance of Head-Of-Line (HOL) blocking, which spoils network performance. In that sense, we present in this paper a simple, efficient strategy for dealing with the HOL blocking that may appear in fat-trees with the aforementioned deterministic routing algorithm. From the results presented in the paper, we can conclude that, in the mentioned environment, our proposal considerably reduces HOL blocking without significantly increasing switch complexity and required silicon area.