A high performance grid-web service framework for the identification of 'conserved sequence tags'
Future Generation Computer Systems
A low-cost strategy to provide full QoS support in Advanced Switching networks
Journal of Systems Architecture: the EUROMICRO Journal
Scheduling solution for the IEEE 802.16 base station
Computer Networks: The International Journal of Computer and Telecommunications Networking
Analyzing Weighted Round Robin policies with a stochastic comparison approach
Computers and Operations Research
LGRR: A new packet scheduling algorithm for differentiated services packet-switched networks
Computer Communications
Impact of bandwidth request schemes for Best-Effort traffic in IEEE 802.16 networks
Computer Communications
A new strategy to manage the InfiniBand arbitration tables
Journal of Parallel and Distributed Computing
VoIP: A comprehensive survey on a promising technology
Computer Networks: The International Journal of Computer and Telecommunications Networking
A survey of MAC based QoS implementations for WiMAX networks
Computer Networks: The International Journal of Computer and Telecommunications Networking
Weighted deficit earliest departure first scheduling
Computer Communications
Integration of admission, congestion, and peak power control in QoS-aware clusters
Journal of Parallel and Distributed Computing
Efficient Gigabit Ethernet Switch Models for Large-Scale Simulation
PADS '10 Proceedings of the 2010 IEEE Workshop on Principles of Advanced and Distributed Simulation
An efficient packet service algorithm for high-speed ATM switches
Computer Communications
IP QoS support in IEEE 802.11b WLANs
Computer Communications
Fair flow control of ABR service by per-VC virtual queuing
Computer Communications
A probabilistic priority scheduling discipline for multi-service networks
Computer Communications
Integrated QoS provision and congestion management for interconnection networks
Euro-Par'07 Proceedings of the 13th international Euro-Par conference on Parallel Processing
A fair spectrum sharing approach in Cognitive Radio Networks
Proceedings of the Second International Conference on Computational Science, Engineering and Information Technology
Fast simulation of background traffic through fair queueing networks
Proceedings of the Winter Simulation Conference
Arbitration of many thousand flows at 100G and beyond
Proceedings of the 2013 Interconnection Network Architecture: On-Chip, Multi-Chip
Improved formal worst-case timing analysis of weighted round robin scheduling for ethernet
Proceedings of the Ninth IEEE/ACM/IFIP International Conference on Hardware/Software Codesign and System Synthesis
Providing multiple hard latency and throughput guarantees for packet switching networks on chip
Computers and Electrical Engineering
| Hi-index | 0.07 |
The authors present the architecture of a general-purpose broadband-ISDN (B-ISDN) switch chip and, in particular, its novel feature: the weighted round-robin cell (packet) multiplexing algorithm and its implementation in hardware. The flow control and buffer management strategies that allow the chip to operate at top performance under congestion are given, and the reason why this multiplexing scheme should be used under those circumstances is explained. The chip architecture and how the key choices were made are discussed. The statistical performance of the switch is analyzed. The critical parts of the chip have been laid out and simulated, thus proving the feasibility of the architecture. Chip sizes of four to ten links with link throughput of 0.5 to 1 Gb/s and with about 1000 virtual circuits per switch have been realized. The results of simulations of the chip are presented