SoCIN: A Parametric and Scalable Network-on-Chip
SBCCI '03 Proceedings of the 16th symposium on Integrated circuits and systems design
Principles and Practices of Interconnection Networks
Principles and Practices of Interconnection Networks
ParIS: a parameterizable interconnect switch for networks-on-chip
SBCCI '04 Proceedings of the 17th symposium on Integrated circuits and system design
Virtual channels in networks on chip: implementation and evaluation on hermes NoC
SBCCI '05 Proceedings of the 18th annual symposium on Integrated circuits and system design
Fitting the router characteristics in NoCs to meet QoS requirements
Proceedings of the 20th annual conference on Integrated circuits and systems design
A latency simulator for many-core systems
Proceedings of the 44th Annual Simulation Symposium
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Networks-on-Chip (NoCs) are recognized as an interconnection architecture with capability of providing scalable performance, which is an important feature for communication in future SoCs (Systems-on-Chip) with high density. Most NoC models proposed in the last years are best effort networks, which offer no guarantees of Quality of Service (QoS) in communication. However, many of the applications envisaged for future SoCs have QoS requirements. In this work, they are presented the deployment of three different mechanisms for providing QoS to a best effort NoC: circuit switching, virtual channels and virtual channels combined with aging scheduling. All the deployments were made in VHDL, and testbenches were used to verify their correct operation. SystemC-based models were also described in order to evaluate the impact of these techniques on the network performance. Results show how the implemented techniques improve the ability of the network in meeting QoS requirements.