Real-time virtual channel flow control
Journal of Parallel and Distributed Computing
A generic architecture for on-chip packet-switched interconnections
DATE '00 Proceedings of the conference on Design, automation and test in Europe
Route packets, not wires: on-chip inteconnection networks
Proceedings of the 38th annual Design Automation Conference
Priority Based Real-Time Communication for Large Scale Wormhole Networks
Proceedings of the 8th International Symposium on Parallel Processing
A Network on Chip Architecture and Design Methodology
ISVLSI '02 Proceedings of the IEEE Computer Society Annual Symposium on VLSI
Guaranteeing the quality of services in networks on chip
Networks on chip
SoCIN: A Parametric and Scalable Network-on-Chip
SBCCI '03 Proceedings of the 16th symposium on Integrated circuits and systems design
xpipes: a Latency Insensitive Parameterized Network-on-chip Architecture For Multi-Processor SoCs
ICCD '03 Proceedings of the 21st International Conference on Computer Design
Bandwidth-Constrained Mapping of Cores onto NoC Architectures
Proceedings of the conference on Design, automation and test in Europe - Volume 2
QNoC: QoS architecture and design process for network on chip
Journal of Systems Architecture: the EUROMICRO Journal - Special issue: Networks on chip
Exploring NoC Mapping Strategies: An Energy and Timing Aware Technique
Proceedings of the conference on Design, Automation and Test in Europe - Volume 1
HERMES: an infrastructure for low area overhead packet-switching networks on chip
Integration, the VLSI Journal - Special issue: Networks on chip and reconfigurable fabrics
Virtual channels in networks on chip: implementation and evaluation on hermes NoC
SBCCI '05 Proceedings of the 18th annual symposium on Integrated circuits and system design
Application-specific buffer space allocation for networks-on-chip router design
Proceedings of the 2004 IEEE/ACM International conference on Computer-aided design
A survey of research and practices of Network-on-chip
ACM Computing Surveys (CSUR)
Adding mechanisms for QoS to a network-on-chip
Proceedings of the 22nd Annual Symposium on Integrated Circuits and System Design: Chip on the Dunes
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This work discusses the adaptation of routers characteristics in Networks-on-Chip to QoS-dependent application requirements, in particular with respect to the fulfillment of task deadlines. The utilization of a flow control mechanism for input buffers with increasing priority for blocked messages and dropping of old packets allows a reduction in the number of missed deadlines. The priorities of messages are dependent on their deadlines, such that the higher priorities are associated with messages that are critical type. Messages blocked by other ones with higher priority have an increment of their priorities after some cycles to avoid starvation. The lower priorities messages can have some of its packets dropped if they have exceeded their respective deadlines. The combination of these strategies with a core placement based on message bandwidth requirements and on message priorities can reduce the number of missed deadlines. This paper shows a design space that can be explored for soft real-time applications.