Reducing test time with processor reuse in network-on-chip based systems
SBCCI '04 Proceedings of the 17th symposium on Integrated circuits and system design
ParIS: a parameterizable interconnect switch for networks-on-chip
SBCCI '04 Proceedings of the 17th symposium on Integrated circuits and system design
Reusing an on-chip network for the test of core-based systems
ACM Transactions on Design Automation of Electronic Systems (TODAES)
A Complete Network-On-Chip Emulation Framework
Proceedings of the conference on Design, Automation and Test in Europe - Volume 1
HERMES: an infrastructure for low area overhead packet-switching networks on chip
Integration, the VLSI Journal - Special issue: Networks on chip and reconfigurable fabrics
LiPaR: A light-weight parallel router for FPGA-based networks-on-chip
GLSVLSI '05 Proceedings of the 15th ACM Great Lakes symposium on VLSI
Design space exploration comparing homogeneous and heterogeneous network-on-chip architectures
SBCCI '05 Proceedings of the 18th annual symposium on Integrated circuits and system design
Fault tolerance overhead in network-on-chip flow control schemes
SBCCI '05 Proceedings of the 18th annual symposium on Integrated circuits and system design
Communication-driven task binding for multiprocessor with latency insensitive network-on-chip
Proceedings of the 2005 Asia and South Pacific Design Automation Conference
Contrasting a NoC and a traditional interconnect fabric with layout awareness
Proceedings of the conference on Design, automation and test in Europe: Proceedings
Reuse-based test access and integrated test scheduling for network-on-chip
Proceedings of the conference on Design, automation and test in Europe: Proceedings
Evaluation of SEU and crosstalk effects in network-on-chip switches
SBCCI '06 Proceedings of the 19th annual symposium on Integrated circuits and systems design
A design methodology for application-specific networks-on-chip
ACM Transactions on Embedded Computing Systems (TECS)
Fitting the router characteristics in NoCs to meet QoS requirements
Proceedings of the 20th annual conference on Integrated circuits and systems design
Router architecture for high-performance NoCs
Proceedings of the 20th annual conference on Integrated circuits and systems design
Proceedings of the 20th annual conference on Integrated circuits and systems design
A predictive NoC architecture for vision systems dedicated to image analysis
EURASIP Journal on Embedded Systems
Crosstalk- and SEU-Aware Networks on Chips
IEEE Design & Test
Mesh-of-tree deterministic routing for network-on-chip architecture
Proceedings of the 18th ACM Great Lakes symposium on VLSI
Invited paper: Network-on-Chip design and synthesis outlook
Integration, the VLSI Journal
Re-examining the use of network-on-chip as test access mechanism
Proceedings of the conference on Design, automation and test in Europe
Dynamic task allocation strategies in MPSoC for soft real-time applications
Proceedings of the conference on Design, automation and test in Europe
Developing mesochronous synchronizers to enable 3D NoCs
Proceedings of the conference on Design, automation and test in Europe
A virtual platform for multiprocessor real-time embedded systems
JTRES '08 Proceedings of the 6th international workshop on Java technologies for real-time and embedded systems
Supporting vertical links for 3D networks-on-chip: toward an automated design and analysis flow
Proceedings of the 2nd international conference on Nano-Networks
On NoC Bandwidth Sharing for the Optimization of Area Cost and Test Application Time
IEICE - Transactions on Information and Systems
Proceedings of the 19th ACM Great Lakes symposium on VLSI
System-on-Chip Test Architectures: Nanometer Design for Testability
System-on-Chip Test Architectures: Nanometer Design for Testability
Performance Evaluation of NoC Architectures for Parallel Workloads
NOCS '09 Proceedings of the 2009 3rd ACM/IEEE International Symposium on Networks-on-Chip
Diagnosis of interconnect shorts in mesh NoCs
NOCS '09 Proceedings of the 2009 3rd ACM/IEEE International Symposium on Networks-on-Chip
Adding mechanisms for QoS to a network-on-chip
Proceedings of the 22nd Annual Symposium on Integrated Circuits and System Design: Chip on the Dunes
Adaptive router architecture based on traffic behavior observability
Proceedings of the 2nd International Workshop on Network on Chip Architectures
Network-on-chip architecture design based on mesh-of-tree deterministic routing topology
International Journal of High Performance Systems Architecture
Proceedings of the 13th International Workshop on Software & Compilers for Embedded Systems
PMCNOC: A Pipelining Multi-channel Central Caching Network-on-chip Communication Architecture Design
Journal of Signal Processing Systems
Proceedings of the Conference on Design, Automation and Test in Europe
Improving the yield of NoC-based systems through fault diagnosis and adaptive routing
Journal of Parallel and Distributed Computing
A new test scheduling algorithm based on Networks-on-Chip as Test Access Mechanisms
Journal of Parallel and Distributed Computing
An ROBDD-based combinatorial method for the evaluation of yield of defect-tolerant systems-on-chip
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
AdNoC case-study for Mpeg4 benchmark: improving performance and saving energy with an adaptive NoC
Proceedings of the 24th symposium on Integrated circuits and systems design
Journal of Electronic Testing: Theory and Applications
Static routing for applications mapped on NoC platform using ant colony algorithms
International Journal of High Performance Systems Architecture
ACO-Based static routing for network-on-chips
ICCSA'12 Proceedings of the 12th international conference on Computational Science and Its Applications - Volume Part I
Optimizing heterogeneous NoC design
Proceedings of the International Workshop on System Level Interconnect Prediction
A novel NoC-based design for fault-tolerance of last-level caches in CMPs
Proceedings of the eighth IEEE/ACM/IFIP international conference on Hardware/software codesign and system synthesis
A fully parallel BIST-based method to test the crosstalk defects on the inter-switch links in NOC
Microelectronics Journal
Routing for applications in NoC using ACO-based algorithms
Applied Soft Computing
Modeling and analysis of fault-tolerant distributed memories for networks-on-chip
Proceedings of the Conference on Design, Automation and Test in Europe
A TDM NoC supporting QoS, multicast, and fast connection set-up
DATE '12 Proceedings of the Conference on Design, Automation and Test in Europe
Expert Systems with Applications: An International Journal
A NOC closed-loop performance monitor and adapter
Microprocessors & Microsystems
NoC-based fault-tolerant cache design in chip multiprocessors
ACM Transactions on Embedded Computing Systems (TECS) - Special Issue on Design Challenges for Many-Core Processors, Special Section on ESTIMedia'13 and Regular Papers
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Networks-on-Chip (NoCs) interconnection architectures to be used in future billion-transistor Systems-on-Chip (SoCs) meet the major communication requirements of these systems, offering, at the same time, reusability, scalability and parallelism in communication. Furthermore, they cope with other issues like power constraints and clock distribution. Currently, there is a number of research works which explore different features of NoCs. In this paper, we present SoCIN, a scalable network based on a parametric router architecture to beused in the synthesis of customized low cost NoCs. The architecture of SoCIN and its router are described, and some synthesis results are presented.