Interconnection Networks: An Engineering Approach
Interconnection Networks: An Engineering Approach
A survey of processors with explicit multithreading
ACM Computing Surveys (CSUR)
Fast Reconfigurable Crossbar Switching in FPGAs
FPL '96 Proceedings of the 6th International Workshop on Field-Programmable Logic, Smart Applications, New Paradigms and Compilers
A High I/O Reconfigurable Crossbar Switch
FCCM '03 Proceedings of the 11th Annual IEEE Symposium on Field-Programmable Custom Computing Machines
SoCIN: A Parametric and Scalable Network-on-Chip
SBCCI '03 Proceedings of the 16th symposium on Integrated circuits and systems design
A survey of research and practices of Network-on-chip
ACM Computing Surveys (CSUR)
ISCA '08 Proceedings of the 35th Annual International Symposium on Computer Architecture
Systematic customization of on-chip crossbar interconnects
ARC'07 Proceedings of the 3rd international conference on Reconfigurable computing: architectures, tools and applications
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Research works have focused on high-performance on-chip interconnections with low cost and energy consumption for the next generation of many-core processors. In the same way, parallel applications will explore thread level parallelism and message-passing communication through a Network-on-Chip (NoC) to perform a high data throughput. Due to the dynamic changing of communication patterns, the goal of this paper is to present the design of Reconfigurable Crossbar Switch for NoC Routers (RCS-NR) capable of adapting topologies on demand. RCS-NR has an optimized architecture, similar area and lower energy consumption (up to 87.41%) relative to a traditional crossbar switch. Furthermore, RCS-NR-based NoC router has a similar area, higher throughput, and it is up to 98.76% more efficient in energy consumption than a conventional NoC.