A High I/O Reconfigurable Crossbar Switch

Authors:
Steve Young;Peter Alfke;Colm Fewer;Scott McMillan;Brandon Blodget;Delon Levi
Affiliations:
-;-;-;-;-;-
Venue:
FCCM '03 Proceedings of the 11th Annual IEEE Symposium on Field-Programmable Custom Computing Machines
Year:
2003

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Abstract

A crossbar switch with 928 inputs and 928 outputs is presented.Switching elements are constructed using logic inthe routing fabric. This approach yields a 16X improvementin logic density compared with using conventionallogic. Normally the routing is fixed. However, in FPGAs,the interconnect is defined by the state of SRAM configurationcells, which are dynamically modifiable. Therefore, theswitch is implemented on an FPGA using partial configurationto modify routing resources during operation. All pathsare synchronously clocked at 155.5 MHz, creating a totalthroughput of 144.3 GBits/s. To maintain constant clock latencyacross all paths, partially configurable delay registersare used. Finally, to enable fast switch updates, the partialreconfiguration controller is implemented in hardware.