Interconnection Networks: An Engineering Approach
Interconnection Networks: An Engineering Approach
Maximal Diagnosis for Wiring Networks
Proceedings of the IEEE International Test Conference on Test: Faster, Better, Sooner
SoCIN: A Parametric and Scalable Network-on-Chip
SBCCI '03 Proceedings of the 16th symposium on Integrated circuits and systems design
DyAD: smart routing for networks-on-chip
Proceedings of the 41st annual Design Automation Conference
NoC Synthesis Flow for Customized Domain Specific Multiprocessor Systems-on-Chip
IEEE Transactions on Parallel and Distributed Systems
BIST for Network-on-Chip Interconnect Infrastructures
VTS '06 Proceedings of the 24th IEEE VLSI Test Symposium
Interconnect Testing for Networks on Chips
VTS '06 Proceedings of the 24th IEEE VLSI Test Symposium
Exploring Fault-Tolerant Network-on-Chip Architectures
DSN '06 Proceedings of the International Conference on Dependable Systems and Networks
On-line Fault Detection and Location for NoC Interconnects
IOLTS '06 Proceedings of the 12th IEEE International Symposium on On-Line Testing
An External Test Approach for Network-on-a-Chip Switches
ATS '06 Proceedings of the 15th Asian Test Symposium
Test Configurations for Diagnosing Faulty Links in NoC Switches
ETS '07 Proceedings of the 12th IEEE European Test Symposium
Fully Adaptive Fault-Tolerant Routing Algorithm for Network-on-Chip Architectures
DSD '07 Proceedings of the 10th Euromicro Conference on Digital System Design Architectures, Methods and Tools
A Lightweight Fault-Tolerant Mechanism for Network-on-Chip
NOCS '08 Proceedings of the Second ACM/IEEE International Symposium on Networks-on-Chip
IEEE Transactions on Computers
Diagnosis of interconnect shorts in mesh NoCs
NOCS '09 Proceedings of the 2009 3rd ACM/IEEE International Symposium on Networks-on-Chip
Testing and diagnosis of interconnects using boundary scan architecture
ITC'88 Proceedings of the 1988 international conference on Test: new frontiers in testing
Bringing communication networks on a chip: test and verification implications
IEEE Communications Magazine
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We propose an effective and low cost method to increase the yield and the lifetime of torus NoCs. The method consists in detecting and diagnosing NoC interconnect faults using BIST structures and activating alternative paths for the faulty links. Alternative paths use the inherent redundancy of the torus topology, thus leading to minimal performance, area, and power overhead. We assume an extended interconnect fault model comprising stuck-at and pairwise shorts within a single link or between any two links in the network. Experimental results for a 3x3 NoC show that the proposed approach can correctly diagnose 93% of all possible interconnect faults and can mitigate 42% of those faults (representing 94.4% of the solvable faults) with a worst case performance penalty of 8% and 1% of area overhead. We also demonstrate the scalability of the method by presenting its application to larger NoCs.