Interconnect Testing for Networks on Chips

Authors:
Khadija Stewart;Spyros Tragoudas
Affiliations:
Southern Illinois University;Southern Illinois University
Venue:
VTS '06 Proceedings of the 24th IEEE VLSI Test Symposium
Year:
2006

Citing 0
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Diagnosis of interconnect shorts in mesh NoCs

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Abstract

A scheme to functionally test the networking infrastructure of a system within a network on chip is presented. A fault model and a test pattern generation and application algorithm that relies on a network simulator are presented. Experimental results demonstrate the impact of the presented algorithm.