Performance Evaluation and Design Trade-Offs for Network-on-Chip Interconnect Architectures
IEEE Transactions on Computers
An event-based monitoring service for networks on chip
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Reuse-based test access and integrated test scheduling for network-on-chip
Proceedings of the conference on Design, automation and test in Europe: Proceedings
Proceedings of the conference on Design, automation and test in Europe: Proceedings
A concurrent testing method for NoC switches
Proceedings of the conference on Design, automation and test in Europe: Proceedings
Toward a scalable test methodology for 2D-mesh Network-on-Chips
Proceedings of the conference on Design, automation and test in Europe
The design and synthesis of a synchronous and distributed MAC protocol for wireless network-on-chip
Proceedings of the 2007 IEEE/ACM international conference on Computer-aided design
NOCS '08 Proceedings of the Second ACM/IEEE International Symposium on Networks-on-Chip
Dual-channel binary-countdown medium access control in wireless network-on-chip
Proceedings of the 2nd international conference on Nano-Networks
MTNet: design of a wireless test framework for heterogeneous nanometer systems-on-chip
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Diagnosis of interconnect shorts in mesh NoCs
NOCS '09 Proceedings of the 2009 3rd ACM/IEEE International Symposium on Networks-on-Chip
Simulation of a signal arbitration algorithm for a sensor array
EUROCAST'07 Proceedings of the 11th international conference on Computer aided systems theory
PMCNOC: A Pipelining Multi-channel Central Caching Network-on-chip Communication Architecture Design
Journal of Signal Processing Systems
Improving the yield of NoC-based systems through fault diagnosis and adaptive routing
Journal of Parallel and Distributed Computing
Optimizing built-in pseudo-random self-testing for network-on-chip switches
Proceedings of the 2012 Interconnection Network Architecture: On-Chip, Multi-Chip Workshop
A switch wrapper design for SNA on-chip-network
ACSAC'05 Proceedings of the 10th Asia-Pacific conference on Advances in Computer Systems Architecture
A practical test scheduling using network-based TAM in network on chip architecture
ACSAC'05 Proceedings of the 10th Asia-Pacific conference on Advances in Computer Systems Architecture
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In this article we present test and verification challenges for system chips that utilize on-chip networks. These SOCs and networks on a chip are introduced, where the NOC is exemplified by Philips' AE THEREAL NOC architecture. We discuss existing test and verification methods for SOCs and NOCs, and show the particular advantages of using an NOC for both testing and verifying the network, and testing and verifying the other components of the SOC. This article is concluded with our experiences with NOCs and a description of ongoing work within Philips in this emerging field.