A practical test scheduling using network-based TAM in network on chip architecture

Authors:
Jin-Ho Ahn;Byung In Moon;Sungho Kang
Affiliations:
Dept. of Electrical & Electronic Eng, Yonsei University, Seoul, Korea;School of Electrical Eng. & Computer Science, Kyungpook National University, Daegu, Korea;Dept. of Electrical & Electronic Eng, Yonsei University, Seoul, Korea
Venue:
ACSAC'05 Proceedings of the 10th Asia-Pacific conference on Advances in Computer Systems Architecture
Year:
2005

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Abstract

It may be impractical to have TAM for test usage only in NoC because it causes enormous hardware overhead. Therefore, the reuse of on-chip networks for TAM is very attractive and logical. In network-based TAM, an effective test scheduling for built-in cores is also important to minimize the total test time. In this paper, we propose a new efficient test scheduling algorithm for NoC based on the reuse of on-chip networks. Experimental results using some ITC’02 benchmark circuits show the proposed algorithm can reduce the test time by about 5 – 20% compared to previous methods. Consequently, the proposed algorithm can be widely used due to its feasibility and practicality.