Reuse-based test access and integrated test scheduling for network-on-chip
Proceedings of the conference on Design, automation and test in Europe: Proceedings
On reliable modular testing with vulnerable test access mechanisms
Proceedings of the 45th annual Design Automation Conference
Re-examining the use of network-on-chip as test access mechanism
Proceedings of the conference on Design, automation and test in Europe
Robust concurrent online testing of network-on-chip-based SoCs
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
System-on-Chip Test Architectures: Nanometer Design for Testability
System-on-Chip Test Architectures: Nanometer Design for Testability
A new test scheduling algorithm based on Networks-on-Chip as Test Access Mechanisms
Journal of Parallel and Distributed Computing
A practical test scheduling using network-based TAM in network on chip architecture
ACSAC'05 Proceedings of the 10th Asia-Pacific conference on Advances in Computer Systems Architecture
Test pin count reduction for NoC-based test delivery in multicore SOCs
DATE '12 Proceedings of the Conference on Design, Automation and Test in Europe
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Network-on-a-Chip (NoC) is becoming a promising paradigm of core-based system. In this paper, we propose a new method for test scheduling in NoC. The mehod is based onthe use of a dedicated routing path for the rest of each core. We show that test scheduling under this approach is NP-complete and present and ILP model for solving small NoC instances. For NoCs with larger number of cores, we present an effecient heuristic. We then improve the heuristic byincluding BISTs and precedence constraints. Eperimental results for the ITC'02 SoC benchmarks show that the new method leadsto substantial reduction on a test application time compared to previous work. The inclusion of BIST tests and precednce constraints provides a comprehensive solution for test scheduling in NoC.