Optimal test access architectures for system-on-a-chip
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Route packets, not wires: on-chip inteconnection networks
Proceedings of the 38th annual Design Automation Conference
Test Wrapper and Test Access Mechanism Co-Optimization for System-on-Chip
Journal of Electronic Testing: Theory and Applications
A Set of Benchmarks fo Modular Testing of SOCs
ITC '02 Proceedings of the 2002 IEEE International Test Conference
Effective and Efficient Test Architecture Design for SOCs
ITC '02 Proceedings of the 2002 IEEE International Test Conference
SoCIN: A Parametric and Scalable Network-on-Chip
SBCCI '03 Proceedings of the 16th symposium on Integrated circuits and systems design
Reusing an on-chip network for the test of core-based systems
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Æthereal Network on Chip: Concepts, Architectures, and Implementations
IEEE Design & Test
Test Scheduling for Network-on-Chip with BIST and Precedence Constraints
ITC '04 Proceedings of the International Test Conference on International Test Conference
A survey of research and practices of Network-on-chip
ACM Computing Surveys (CSUR)
Wrapper Design for the Reuse of Networks-on-Chip as Test Access Mechanism
ETS '06 Proceedings of the Eleventh IEEE European Test Symposium
Optimization of NoC Wrapper Design under Bandwidth and Test Time Constraints
ETS '07 Proceedings of the 12th IEEE European Test Symposium
DfT for the Reuse of Networks-on-Chip as Test Access Mechanism
VTS '07 Proceedings of the 25th IEEE VLSI Test Symmposium
Crosstalk- and SEU-Aware Networks on Chips
IEEE Design & Test
On reliable modular testing with vulnerable test access mechanisms
Proceedings of the 45th annual Design Automation Conference
A new test scheduling algorithm based on Networks-on-Chip as Test Access Mechanisms
Journal of Parallel and Distributed Computing
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Existing work on testing NoC-based systems advocates to reuse the on-chip network itself as test access mechanism (TAM) to transport test data to/from embedded cores. While this methodology obviously reduces the routing cost when compared to the case that dedicated test buses are introduced as TAMs, it is not clear whether it is beneficial in terms of other important factors that significantly affect test cost, e.g., testing time, test control complexity and test reliability. As a result, in this paper, we re-examine the issue of using NoC as TAM in order to facilitate designers to construct a cost-effective system test architecture based on their requirements.