DfT for the Reuse of Networks-on-Chip as Test Access Mechanism

Authors:
Alexandre M. Amory;Frederico Ferlini;Marcelo Lubaszewski;Fernando Moraes
Affiliations:
UFRGS Federal University, Brazil;PUCRS Catholic University, Brazil;UFRGS Federal University, Brazil;PUCRS Catholic University, Brazil
Venue:
VTS '07 Proceedings of the 25th IEEE VLSI Test Symmposium
Year:
2007

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Abstract

This paper presents new DfT modules required to use networks-on- chip as test access mechanism. We demonstrate that the proposed DfT modules can be also implemented on top of low cost networks-on-chip, i.e. networks without complex services. The DfT modules, which consist of test wrappers and test pin interfaces, are designed such that both the tester and CUTs transport test data unaware of the network. We analyse the DfT modules in terms of silicon area and test time, considering different network and test configurations.