A switch wrapper design for SNA on-chip-network

Authors:
Jiho Chang;Jongsu Yi;JunSeong Kim
Affiliations:
School of Electrical and Electronics Engineering, Chung-Ang University, Seoul, Korea;School of Electrical and Electronics Engineering, Chung-Ang University, Seoul, Korea;School of Electrical and Electronics Engineering, Chung-Ang University, Seoul, Korea
Venue:
ACSAC'05 Proceedings of the 10th Asia-Pacific conference on Advances in Computer Systems Architecture
Year:
2005

Citing 3
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Abstract

In this paper we present a design of a switch wrapper as a component of SNA (SoC network architecture), which is an efficient on-chip-network compared to a shared bus architecture in a SoC. The SNA uses crossbar routers to provide the increasing demand on communication bandwidth within a single chip. A switch wrapper for SNA is located between a crossbar router and IPs connecting them together. It carries out a mode of routing to assist crossbar routers and executes protocol conversions to provide compatibility in IP reuse. A switch wrapper consists of a direct router, two AHB-SNP converters, two interface sockets and a controller module. We implement it in VHDL. Using ModelSim simulation, we confirm the functionality of the switch wrapper. We synthesize it using a Xilinx Virtex2 device to determine resource requirements: The switch wrapper seems to occupy appropriate spaces, about 900 gates, considering that a single SNA crossbar router costs about 20,000 gates.