A generic architecture for on-chip packet-switched interconnections
DATE '00 Proceedings of the conference on Design, automation and test in Europe
Energy efficient real-time scheduling
Proceedings of the 2001 IEEE/ACM international conference on Computer-aided design
A Study on Communication Issues for Systems-on-Chip
Proceedings of the 15th symposium on Integrated circuits and systems design
A Network on Chip Architecture and Design Methodology
ISVLSI '02 Proceedings of the IEEE Computer Society Annual Symposium on VLSI
A low-power in-order/out-of-order issue queue
ACM Transactions on Architecture and Code Optimization (TACO)
Network on Chip Simulations for Benchmarking
IWSOC '04 Proceedings of the System-on-Chip for Real-Time Applications, 4th IEEE International Workshop
Bringing communication networks on a chip: test and verification implications
IEEE Communications Magazine
| Hi-index | 0.00 |
We present a simulation based study of an arrangement consisting of a sensor array, connected to a set of signal processing units (PUs), capable to be reconfigured in real time, depending on the signal type and processing requirements. The signal issued by a sensor is conveyed by means of an arbitration algorithm to a proper PU, so that the number of its state transitions should decrease. The algorithm also ensures a high throughput of the signals to be processed. The system includes queues at the PU level, to lower data loss. The functioning of the PUs is based upon two strategies: maximising task charge and standby state period, to maintain the highest number of spare PUs in order to decrease the reconfiguration actions and the associate power penalty. The sensors are capable to issue signals with variable frequency in time, a factor considered when prioritising among concomitantly generated signals.