Analyzing On-Chip Communication in a MPSoC Environment
Proceedings of the conference on Design, automation and test in Europe - Volume 2
Proceedings of the conference on Design, automation and test in Europe - Volume 2
Reducing test time with processor reuse in network-on-chip based systems
SBCCI '04 Proceedings of the 17th symposium on Integrated circuits and system design
Reusing an on-chip network for the test of core-based systems
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Fault tolerance overhead in network-on-chip flow control schemes
SBCCI '05 Proceedings of the 18th annual symposium on Integrated circuits and system design
Modeling and analysis of the system bus latency on the SoC platform
Proceedings of the 2006 international workshop on System-level interconnect prediction
Proceedings of the conference on Design, automation and test in Europe: Proceedings
HIBI Communication Network for System-on-Chip
Journal of VLSI Signal Processing Systems
Benchmarking mesh and hierarchical bus networks in system-on-chip context
Journal of Systems Architecture: the EUROMICRO Journal
A Hybrid Ring/Mesh Interconnect for Network-on-Chip Using Hierarchical Rings for Global Routing
NOCS '07 Proceedings of the First International Symposium on Networks-on-Chip
Toward a scalable test methodology for 2D-mesh Network-on-Chips
Proceedings of the conference on Design, automation and test in Europe
Flexible and abstract communication and interconnect modeling for MPSoC
Proceedings of the 2009 Asia and South Pacific Design Automation Conference
Evaluating SoC Network Performance in MPEG-4 Encoder
Journal of Signal Processing Systems
THIN: a new hierarchical interconnection network-on-chip for SOC
ICA3PP'07 Proceedings of the 7th international conference on Algorithms and architectures for parallel processing
Simulation of a signal arbitration algorithm for a sensor array
EUROCAST'07 Proceedings of the 11th international conference on Computer aided systems theory
Priority-based packet communication on a bus-shaped structure for FPGA-systems
Proceedings of the Conference on Design, Automation and Test in Europe
Specification and verification of a MPI implementation for a MP-SoC
ICTAC'10 Proceedings of the 7th International colloquium conference on Theoretical aspects of computing
Turbo NOC: a framework for the design of network-on-chip-based turbo decoder architectures
IEEE Transactions on Circuits and Systems Part I: Regular Papers
GNLS: a hybrid on-chip communication architecture for SoC designs
International Journal of High Performance Systems Architecture
Benchmarking mesh and hierarchical bus networks in system-on-chip context
SAMOS'05 Proceedings of the 5th international conference on Embedded Computer Systems: architectures, Modeling, and Simulation
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Present days cores composing a System-on-Chip might be interconnected by means of both dedicated channels or shared buses. Nevertheless, future systems will have strong requirements on reusability and communication performance, which will constrain the use of such interconnect systems. An emerging approach, the Networks-on-Chip (NOCs), will potentially fulfill those requirements, because NOCs are reusable and their communication performance gracefully scales with the system growth. However, it is still not clear when the use of NOCs will become mandatory. This work introduces some studies to define the switching point when NOCs become the preferred communication architecture. A bus and a NOC are modeled and compared by using a set of mathematical models.