THIN: a new hierarchical interconnection network-on-chip for SOC

Authors:
Baojun Qiao;Feng Shi;Weixing Ji
Affiliations:
School of Computer Science and Technology, Beijing Institute of Technology, Beijing, China and Institute of Data and Knowledge Engineering, Henan University, Kaifeng, Henan, China;School of Computer Science and Technology, Beijing Institute of Technology, Beijing, China;School of Computer Science and Technology, Beijing Institute of Technology, Beijing, China
Venue:
ICA3PP'07 Proceedings of the 7th international conference on Algorithms and architectures for parallel processing
Year:
2007

Citing 9
Cited 2

A recursively scalable network VLSI implementation

Future Generation Computer Systems
Hierarchical Interconnection Networks for Multicomputer Systems

IEEE Transactions on Computers
A generic architecture for on-chip packet-switched interconnections

DATE '00 Proceedings of the conference on Design, automation and test in Europe
Route packets, not wires: on-chip inteconnection networks

Proceedings of the 38th annual Design Automation Conference
Interconnection Networks: An Engineering Approach

Interconnection Networks: An Engineering Approach
Networks on Chips: A New SoC Paradigm

Computer
Multicast Communication in Multicomputer Networks

IEEE Transactions on Parallel and Distributed Systems
A Study on Communication Issues for Systems-on-Chip

Proceedings of the 15th symposium on Integrated circuits and systems design
A Network on Chip Architecture and Design Methodology

ISVLSI '02 Proceedings of the IEEE Computer Society Annual Symposium on VLSI

HiRA: A methodology for deadlock free routing in hierarchical networks on chip

NOCS '09 Proceedings of the 2009 3rd ACM/IEEE International Symposium on Networks-on-Chip
Topological properties of hierarchical interconnection networks: a review and comparison

Journal of Electrical and Computer Engineering

Quantified Score

Hi-index	0.00

Visualization

Abstract

On-chip communication architectures can have a great influence on the speed and area of System-on-Chip (SOC) designs. A new chip design paradigm called Network-on-Chip (NOC) offers a promising architectural choice for future SOC. Focusing on decreasing node degree, reducing links and shortening diameter, a new NOC, named Triple-based Hierarchical Interconnection Network (THIN), is presented in this paper. The topology of THIN is very simple and it has obviously hierarchical, symmetric and scalable characteristic. The network properties and zero-load latency were studied and compared with 2-D mesh and Hypercube. The results show THIN is superior to 2-D mesh and Hypercube to construct interconnection network for SOC, when the network size is not very large. A new tree-based multicast routing algorithm in THIN is proposed. Thorough analyses and experiments based on different multicast implementation schemes are conducted. The results do confirm the advantage of our scheme over unicast-based and path-based multicast schemes.