HiRA: A methodology for deadlock free routing in hierarchical networks on chip

Authors:
Rickard Holsmark;Shashi Kumar;Maurizio Palesi;Andres Mejia
Affiliations:
Dept. of Electronics and Computer Engineering, Jönköping University, Sweden;Dept. of Electronics and Computer Engineering, Jönköping University, Sweden;Dept. of Computer Science and Telecommunications Engineering, University of Catania, Italy;Dept. of Computing Engineering, Technical University of Valencia, Spain
Venue:
NOCS '09 Proceedings of the 2009 3rd ACM/IEEE International Symposium on Networks-on-Chip
Year:
2009

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Abstract

Complexity of designing large and complex NoCs can be reduced/managed by using the concept of hierarchical networks. In this paper, we propose a methodology for design of deadlock free routing algorithms for hierarchical networks, by combining routing algorithms of component subnets. Specifically, our methodology ensures reachability and deadlock freedom for the complete network if routing algorithms for subnets are deadlock free. We evaluate and compare the performance of hierarchical routing algorithms designed using our methodology with routing algorithms for corresponding flat networks. We show that hierarchical routing, combining best routing algorithm for each subnet, has a potential for providing better performance than using any single routing algorithm. This is observed for both synthetic as well as traffic from real applications. We also demonstrate, by measuring jitter in throughput, that hierarchical routing algorithms leads to smoother flow of network traffic. A router architecture that supports scalable table-based routing is briefly outlined.