Bandwidth-Constrained Mapping of Cores onto NoC Architectures
Proceedings of the conference on Design, automation and test in Europe - Volume 2
×pipesCompiler: A Tool for Instantiating Application Specific Networks on Chip
Proceedings of the conference on Design, automation and test in Europe - Volume 2
NoC Synthesis Flow for Customized Domain Specific Multiprocessor Systems-on-Chip
IEEE Transactions on Parallel and Distributed Systems
A low-power crossroad switch architecture and its core placement for network-on-chip
ISLPED '05 Proceedings of the 2005 international symposium on Low power electronics and design
Zikimi: A Case Study in Micro Kernel Design for Multimedia Applications
Multimedia Tools and Applications
ACM Transactions on Design Automation of Electronic Systems (TODAES)
HiRA: A methodology for deadlock free routing in hierarchical networks on chip
NOCS '09 Proceedings of the 2009 3rd ACM/IEEE International Symposium on Networks-on-Chip
The era of many-modules SoC: revisiting the NoC mapping problem
Proceedings of the 2nd International Workshop on Network on Chip Architectures
Throughput-oriented NoC topology generation and analysis for high performance SoCs
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
A modeling tool for simulating and design of on-chip network systems
Microprocessors & Microsystems
Cost-effective slack allocation for lifetime improvement in NoC-based MPSoCs
Proceedings of the Conference on Design, Automation and Test in Europe
A case for lifetime-aware task mapping in embedded chip multiprocessors
CODES/ISSS '10 Proceedings of the eighth IEEE/ACM/IFIP international conference on Hardware/software codesign and system synthesis
Cost-effective lifetime and yield optimization for NoC-based MPSoCs
ACM Transactions on Design Automation of Electronic Systems (TODAES)
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We present a chip-set for digital video processing in a consumer television receiver or set-top box. Key aspects of the chip-set are a high flexibility and programmability of multi-window features with multiple Teletext (TXT) pages, Internet pages and video processing up to three live windows. The chip-set contains a microcontroller with peripherals featuring a.o. pixel-based graphics (GFX) and telecommunication interfaces. The second chip is a video processor containing a number of flexible coprocessors for horizontal and vertical scaling, sharpness enhancement, adaptive temporal noise reduction, blending of graphics, mixing of multiple video streams, and 100 Hz up-conversion