An Optimal Shortest-Path Routing Policy for Network Computers with Regular Mesh-Connected Topologies
IEEE Transactions on Computers
Segmented bus design for low-power systems
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Gated-Vdd: a circuit technique to reduce leakage in deep-submicron cache memories
ISLPED '00 Proceedings of the 2000 international symposium on Low power electronics and design
Route packets, not wires: on-chip inteconnection networks
Proceedings of the 38th annual Design Automation Conference
Traffic analysis for on-chip networks design of multimedia applications
Proceedings of the 39th annual Design Automation Conference
Drowsy caches: simple techniques for reducing leakage power
ISCA '02 Proceedings of the 29th annual international symposium on Computer architecture
Design theory and implementation for low-power segmented bus systems
ACM Transactions on Design Automation of Electronic Systems (TODAES)
IEEE Transactions on Parallel and Distributed Systems
Orion: a power-performance simulator for interconnection networks
Proceedings of the 35th annual ACM/IEEE international symposium on Microarchitecture
A survey of techniques for energy efficient on-chip communication
Proceedings of the 40th annual Design Automation Conference
A Methodology for Designing Efficient On-Chip Interconnects on Well-Behaved Communication Patterns
HPCA '03 Proceedings of the 9th International Symposium on High-Performance Computer Architecture
Leakage power modeling and optimization in interconnection networks
Proceedings of the 2003 international symposium on Low power electronics and design
Efficient Synthesis of Networks On Chip
ICCD '03 Proceedings of the 21st International Conference on Computer Design
Bandwidth-Constrained Mapping of Cores onto NoC Architectures
Proceedings of the conference on Design, automation and test in Europe - Volume 2
×pipesCompiler: A Tool for Instantiating Application Specific Networks on Chip
Proceedings of the conference on Design, automation and test in Europe - Volume 2
SUNMAP: a tool for automatic topology selection and generation for NoCs
Proceedings of the 41st annual Design Automation Conference
Exploiting the Routing Flexibility for Energy/Performance Aware Mapping of Regular NoC Architectures
DATE '03 Proceedings of the conference on Design, Automation and Test in Europe - Volume 1
Design-Space Exploration of Power-Aware On/Off Interconnection Networks
ICCD '04 Proceedings of the IEEE International Conference on Computer Design
Joint Application Mapping/Interconnect Synthesis Techniques for Embedded Chip-Scale Multiprocessors
IEEE Transactions on Parallel and Distributed Systems
NoC Synthesis Flow for Customized Domain Specific Multiprocessor Systems-on-Chip
IEEE Transactions on Parallel and Distributed Systems
Performance Evaluation and Design Trade-Offs for Network-on-Chip Interconnect Architectures
IEEE Transactions on Computers
A low-power crossroad switch architecture and its core placement for network-on-chip
ISLPED '05 Proceedings of the 2005 international symposium on Low power electronics and design
Design, Synthesis, and Test of Networks on Chips
IEEE Design & Test
Analysis and Implementation of Practical, Cost-Effective Networks on Chips
IEEE Design & Test
Area - Time - Power and Design effort: the basic tradeoffs in Application Specific Systems
ASAP '05 Proceedings of the 2005 IEEE International Conference on Application-Specific Systems, Architecture Processors
Energy-aware mapping for tile-based NoC architectures under performance constraints
ASP-DAC '03 Proceedings of the 2003 Asia and South Pacific Design Automation Conference
Low-power network-on-chip for high-performance SoC design
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Proceedings of the 43rd annual Design Automation Conference
EURO-PDP'00 Proceedings of the 8th Euromicro conference on Parallel and distributed processing
Chip-set for video display of multimedia information
IEEE Transactions on Consumer Electronics
Architectural energy optimization by bus splitting
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Implementation of a self-timed segmented bus
IEEE Design & Test
No cache-coherence: a single-cycle ring interconnection for multi-core L1-NUCA sharing on 3D chips
Proceedings of the 46th Annual Design Automation Conference
Reliable network-on-chip design for multi-core system-on-chip
The Journal of Supercomputing
Network-on-Chip interconnect for pairing-based cryptographic IP cores
Journal of Systems Architecture: the EUROMICRO Journal
Hierarchical circuit-switched NoC for multicore video processing
Microprocessors & Microsystems
An energy-aware online task mapping algorithm in NoC-based system
The Journal of Supercomputing
Supporting faulty banks in NUCA by NoC assisted remapping mechanisms
The Journal of Supercomputing
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As the number of cores on a chip increases, power consumed by the communication structures takes a significant portion of the overall power budget. In this article, we first propose a circuit-switched interconnection architecture which uses crossroad switches to construct dedicated channels dynamically between any pairs of cores for nonhuge application-specific SoCs. The structure of the crossroad switch is simple, which can be regarded as a NoC-lite router, and we can easily construct a low-power on-chip network with these switches by a system-level design methodology. We also present the design methodology to tailor the proposed interconnection architecture to low-power structures by two proposed optimization schemes with profiled communication characteristics. The first scheme is power-aware topology construction, which can build low-power application-specific interconnection topologies. To further reduce the power consumption, we propose the second optimization scheme to predetermine the operating mode of dual-mode switches in the NoC at runtime. We evaluate several interconnection techniques, and the results show that the proposed architecture is more low-power and high-performance than others under some constraints and scale boundaries. We take multimedia applications as case studies, and experimental results show the power savings of power-aware topology approximate to 49% of the interconnection architecture. The power consumption can be further reduced approximately 25% by applying partially dedicated path mechanism.