Route packets, not wires: on-chip inteconnection networks
Proceedings of the 38th annual Design Automation Conference
Analysis of power consumption on switch fabrics in network routers
Proceedings of the 39th annual Design Automation Conference
A Network on Chip Architecture and Design Methodology
ISVLSI '02 Proceedings of the IEEE Computer Society Annual Symposium on VLSI
Proceedings of the conference on Design, automation and test in Europe - Volume 1
Principles and Practices of Interconnection Networks
Principles and Practices of Interconnection Networks
A Network Traffic Generator Model for Fast Network-on-Chip Simulation
Proceedings of the conference on Design, Automation and Test in Europe - Volume 2
Supporting task migration in multi-processor systems-on-chip: a feasibility study
Proceedings of the conference on Design, automation and test in Europe: Proceedings
A survey of research and practices of Network-on-chip
ACM Computing Surveys (CSUR)
Automatic run-time extraction of communication graphs from multithreaded applications
CODES+ISSS '06 Proceedings of the 4th international conference on Hardware/software codesign and system synthesis
Proceedings of the 20th annual conference on Integrated circuits and systems design
Incremental run-time application mapping for homogeneous NoCs with multiple voltage levels
CODES+ISSS '07 Proceedings of the 5th IEEE/ACM international conference on Hardware/software codesign and system synthesis
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Application mapping for chip multiprocessors
Proceedings of the 45th annual Design Automation Conference
User-aware dynamic task allocation in networks-on-chip
Proceedings of the conference on Design, automation and test in Europe
Outstanding research problems in NoC design: system, microarchitecture, and circuit perspectives
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
On-Chip Networks
An analysis of on-chip interconnection networks for large-scale chip multiprocessors
ACM Transactions on Architecture and Code Optimization (TACO)
ORION 2.0: a fast and accurate NoC power and area model for early-stage design space exploration
Proceedings of the Conference on Design, Automation and Test in Europe
State observer controller design for packets flow control in networks-on-chip
The Journal of Supercomputing
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With the development of the semiconductor technology, more processors can be integrated onto a single chip. Network-on-Chip is an efficient communication solution for many-core system. However, enhancing performance with lower energy consumption is still a challenge. One critical issue is mapping applications to NoC. This work proposed an online mapping method, which optimizes task mapping algorithm to reduce communication energy consumption. The communication status of applications at runtime is analyzed first. Then, the algorithm computes the mapping placement dynamically and implements the real-time mapping online. Experimental results based on simulation show that the algorithm proposed in this article can achieve more than 20% communication energy saving compared with first fit mapping and nearest neighbor mapping. The migration cost caused by the remapping process is also considered, and can be calculated at the runtime to estimate the effect of remapping.